EZ-PD™ CCG7D Automotive USB Type-C and Buck-boost Controller
Dual-port
Applications
Table 5
RSE GPIO pin mapping for application diagram in Figure 13
Port 0: Display and charger port
Port 1: Charge only port
Pin #
Pin name
Function
GPIO
RSE
18
CSN_0_GPIO0
Port 0: Hot Plug Detect
P0.0
P0_HPD
Port 0: CSP pin on ground side to implement VBAT
to GND short circuit protection
19
20
21
22
CSP_0_GPIO1
GPIO2
P0.1
P0.2
P0.3
P0.4
P0_VBAT_CSP
P0_VBAT_FET
I2CM_SCL
Port 0: GPIO to disable the FET for VBAT to GND
short circuit protection
I2C Master Clock (SCL) for controlling the Display
port Mux
I2C Master Data (SDA) for controlling the Display
port Mux
GPIO3
GPIO4
I2CM_SDA
23
24
DP_0_GPIO5
DM_0_GPIO6
GPIO, available for system level function
GPIO, available for system level function
P1.0
P1.1
GPIO
GPIO
Port 1: USB DM of Type-C port. Supports BC 1.2, QC,
Apple Charging and AFC
26
27
29
30
31
DM_1_GPIO7
DP_1_GPIO8
GPIO9
P1.2
P1.3
P2.0
P2.1
P1.4
P1_DM
P1_DP
Port 1: USB DP of Type-C port. Supports BC 1.2, QC,
Apple Charging and AFC
HPI_SDA
[BILLBOARD]
HPI_SCL
[BILLBOARD]
HPI data (SDA)
HPI clock (SCL)
GPIO10
Port 1: GPIO to disable the FET for VBAT to GND
short circuit protection
GPIO11
P1_VBAT_FET
P1_VBAT_CSP
HPI_INT
Port 1: CSP pin on ground side to implement VBAT
to GND short circuit protection
32
33
CSP_1_GPIO12
P1.5
P1.6
CSN_1_GPIO13 HPI INT
LIN TX pin
56
57
GPIO14
Connect to the host programmer’s SWDIO (data) for
programming the CCG7D device
P3.0
P3.1
LIN_TX
LIN_RX
LIN RX pin
GPIO15
Connect to the host programmer’s SWDCLK (clock)
for programming the CCG7D
58
59
60
GPIO16
GPIO17
GPIO18
LIN Transceiver enable
Port 1: Thermistor
Port 0: Thermistor
P3.2
P3.3
P3.4
LIN_TXR_EN
P1_NTC[0]
P0_NTC[0]
Datasheet
27
002-28172 Rev. *N
2023-01-31
INFINEON [ Infineon ]
