AN985B/BX
Pin Description
6
Pin Description
Table 3
Pin Definitions and Functions
Pin or Ball Name
No.
Pin
Type
Buffer
Type
Function
PCI Interface
24
INTA#
RST#
O/D
I
CARDBUS Interrupt Request
AN985B/BX asserts this signal when one of the interrupt
events occurs.
25
CARDBUS Signal to Initialize the AN985B/BX
The active reset signal should be sustained for at least
100µs to guarantee that the AN985B/BX has completed the
initializing activity. During the reset period, all the output
pins of AN985B/BX will be set to tri-state and all the O/D
pins are floated.
27
29
CLK
I
This CARDBUS Clock Inputs to AN985B/BX for
CARDBUS Relative Circuits as the Synchronized
Timing Base with CARDBUS
The Bus signals are recognized on the rising edge of
CARDBUS-CLK. In order to let the network operate
properly, the frequency range of the CARDBUS-CLK is
limited to between 20 MHz and 33 MHz when the network
is operating.
CARDBUS Bus Granted
This signal indicates that the bus request of AN985B/BX
has been accepted.
CARDBUS Bus Request
Bus master device wants to get bus access right
GNT#
REQ#
I
30
31
O
PME#/CSTSCH I/O
G
Power Management Event
The Power Management Event signal is an open drain,
active low signal for CARDBUS(PME#). When WOL-bit 18
of CSR is set into “1”, this means that the AN985B/BX is set
into Wake On LAN mode. In this mode, when the
AN985B/BX receives a Magic Packet frame from network
then the AN985B/BX will active this signal too. In the Wake
On LAN mode, when LWS-bit (bit 17) of CSR18 is set to “1”
this means the LAN-WAKE signal is a HP-style signal,
otherwise it is an IBM-style signal.
Data Sheet
13
Rev. 1.51, 2005-11-30
INFINEON [ Infineon ]
