AN985B/BX
Features
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Supports PC98 wake on LAN
FIFO
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Provides two independent long FIFOs with 2k bytes each for transmission and reception
Pre-fetch up to two transmit packets to minimize inter frame gap (IFG) to 0.96 µs
Retransmit collided packet without reload from host memory within 64 bytes
Automatically retransmit FIFO under-run packet with maximum drain threshold until 3 times retry failure and
that will not influence the registers and transmit threshold of next packet
CARDBUS I/F
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Provides 32-bit PCI bus master data transfer
Supports CARDBUS clock with frequency from 0 Hz to 33 MHz
Supports network operation with CARDBUS system clock from 20 MHz to 33 MHz
Performance meter, CARDBUS bus master latency timer, for tuning the threshold to enhance performance
Burst transmit packet interrupt and transmit/receive early interrupt to reduce host CPU utilization
Memory-read, memory-read-line, memory-read-multiple, memory-write, memory-write-and-invalidate
command while being bus master
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Supports big or little endian byte ordering
EEPROM/Boot ROM I/F
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Write-able Flash ROM and EPROM as boot ROM with size up to 128 KB
CARDBUS to access boot ROM by byte, word, or double word
Re-write Flash boot ROM through I/O port by programming register
Serial interface for read/write 93C46/66 EEPROM
Automatically loads device ID, vendor ID, subsystem ID, subsystem vendor ID, Maximum-Latency, and
Minimum-Grand from the 64 byte contents of 93C46/66 after PCI reset de-asserted in PCI environment
CIS data is recalled from 93C66 to AN985B/BX PC internal SRAM to speed up CIS access in CARDBUS
environment
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MAC/Physical
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Integrates the whole Physical layer functions of 100BASE-TX and 10BASE-T
Full -duplex operation on both 100 Mbit/s and 10 Mbit/s modes
Auto-negotiation (NWAY) function of full/half duplex operation for both 10 and 100 Mbit/s
Transmits wave-shaper, receive filters, and adaptive equalizer
MLT-3 transceivers with DC restoration for Base-line wander compensation
MAC and Transceiver (TXCVR) loop-back modes for diagnostic
Built in Stream Cipher Scrambler/ De-scrambler and 4B/5B encoder/decoder
External transmitting transformer with turn ratio 1:1
External receiving transformer with turn ratio 1:1
LED Display
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3 LEDs display scheme provided:
– 100 Mbit/s (on) or Speed 10 (off)
– Link (keeps on when link ok) or Activity (will be blinking with 10 Hz when receiving or transmitting but not
collision)
– FD (keeps on when in Full duplex mode) or Collision (will be blinking with 20 Hz when colliding)
4 LEDs displayed scheme provided:
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– 100 Mbit/s and Link (keep on when link and 100 Mbit/s)
– 10 Mbit/s and Link (keep on when link and 10 Mbit/s)
– Activity (will be blinking with 10 Hz when receiving or transmitting but not collision)
– FD (keeps on when in Full duplex mode) or Collision (will be blinking with 20 Hz when colliding)
Miscellaneous
128-pin QFP package for CARDBUS interface.
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Data Sheet
9
Rev. 1.51, 2005-11-30
INFINEON [ Infineon ]
