AN985B/BX
Pin Description
Table 3
Pin Definitions and Functions (cont’d)
Pin or Ball Name
No.
Pin
Type
Buffer
Type
Function
60
61
63
IRDY#
TRDY#
DEVSEL#
I/O
I/O
I/O
Master Device is Ready to Data Transaction
Slave Device is Ready to Data Transaction
Device Select
Device select, target is driving to indicate the address is
decoded
64
65
STOP#
PERR#
I/O
I/O
Stop the Current Transaction
Target device requests the master device to stop the
current transaction
Data Parity Error
Data parity error is detected, driven by the agent receiving
data
66
68
SERR#
PAR
O/D
I/O
Address Parity Error
Parity
Parity, even parity (AD [31:0] + C/BE [3:0]); master drives
par for address and write data phas; target drives par for
read data phase
92
Clk-run
I/O,
O/D
Clock Run for CARDBUS System
In the normal operation situation, Host should assert this
signal to indicate to AN985B/BX about the normal situation.
On the other hand, when Host deasserts this signal the
clock is going down to a non-operating frequency. When
AN985B/BX recognizes the deasserted status of clk-run,
then it will assert clk-run to request Host to maintain the
normal clock operation. When the clk-run function is
disabled then the AN985B/BX will set clk-run in tri-state.
BOOTROM/EEPROM Interface
98
99
BrA0
BrA1
BrA2
BrA3
BrA4
BrA5
BrA6
BrA7
I/O
ROM Data Bus
Provides up to 128kB EPROM or Flash-ROM application
space.
100
101
106
108
109
110
112
113
126
127
128
1
BrA8
BrA9
BrA10
BrA11
BrA12
BrA13
BrA14
BrA15
BrA16
2
3
105
Data Sheet
15
Rev. 1.51, 2005-11-30
INFINEON [ Infineon ]
