IN16C1054
Table 10 shows ISR[7:0] bit settings.
Table 10: Interrupt Status Register Description
Bit
Symbol
Description
7
ISR[7]
FCR[0]/256 TX FIFO Empty.
When 256-byte FIFO mode is disabled (default).
Mirror the content of FCR[0].
When 256-byte FIFO mode is enabled.
0 : 256-byte TX FIFO is full.
1 : 256-byte TX FIFO is not full.
When TCR is ‘00h’, there are two situations of TX FIFO full and TX FIFO empty. If 256 TX
empty bit is ‘1’, it means TX FIFO is empty and if ‘0’, it means 256 bytes character is fully
stored in TX FIFO.
6
ISR[6]
FCR[0]/256 RX FIFO Full.
When 256-byte FIFO mode is disabled (default).
Mirror the content of FCR[0].
When 256-byte FIFO mode is enabled.
0 : 256-byte RX FIFO is not full.
1 : 256-byte RX FIFO is full.
When RCR is ‘00h’, there are two situations of RX FIFO full and RX FIFO empty. If 256 RX
empty bit is ‘1’, it means 256 bytes character is fully stored in RX FIFO and if ‘0’, it means
RX FIFO is empty.
Table 10: Interrupt Status Register Description…continued
Bit
Interrupt Priority List and Reset Functions
Priority Interrupt Type Interrupt Source
5:0
Interrupt Reset Control
―
00_0001
00_0110
00_1100
―
1
None
None
Receiver Line Status
Receive Data Available
OE, PE, FE, BI
Receiver data available, reaches
trigger level.
Reading the LSR.
Reading the RBR or FIFO
falls below trigger level.
Reading the RBR.
2
00_0100
00_0010
2
3
Character Timeout Indi- At least one data is in RX FIFO and
cation
there are no more data in FIFO during
four character time.
Transmit Holding
Register Empty
When THR is empty or TX FIFO Reading the ISR or write
passes
data on THR.
above trigger level (FIFO enable).
CTS#, DSR#, DCD#, RI#
00_0000
01_0000
4
5
Modem Status
Reading the MSR.
Receive Xoff or Special Detection of
a
Xoff or special Reading the ISR.
Character
character.
10_0000
6
RTS#, CTS# Status
during Auto RTS/CTS
flow control
RTS# pin or CTS# pin change state Reading the ISR.
from ‘0’ to ‘1’.
7.5 FIFO Control Register (FCR, Page 0)
FCR is used for enabling the FIFOs, clearing the FIFOs, setting transmit/receive FIFO
trigger level, and selecting the DMA modes. Table 11 shows FCR bit settings.
Rev. 00
IKSEMICON [ IK SEMICON CO., LTD ]
