IN16C1054
7.8 Line Status Register (LSR, Page 0)
LSR provides the status of data transfers between the UART and the CPU. When LSR is
read, LSR[4:2] reflect the error bits (BI, FE, PE) of the character at the top of the RX
FIFO. The errors in a character are identified by reading LSR and then reading RBR.
Reading LSR does not cause an increment of the RX FIFO read pointer. The RX FIFO
read pointer is incremented by reading the RBR. Table 14 shows LSR bit settings.
Table 14: Line Status Register Description
Bit
Symbol Description
7
LSR[7]
RX FIFO data error Indicator.
0 : No RX FIFO error (default).
1 : At least one parity error, framing error, or break indication is in the
RX FIFO. This bit is cleared when there is no more error in any of
characters in the RX FIFO.
6
5
LSR[6]
LSR[5]
THR and TSR Empty Indicator.
0 : THR or TSR is not empty.
1 : THR and TSR are empty.
THR Empty Indicator.
0 : THR is not empty.
1 : THR is empty. It indicates that the UART is ready to accept a new
character for transmission. In addition, it uses the UART to gener-
ate an interrupt to the CPU when the THR empty interrupt enable
is set to ‘1’.
4
LSR[4]
Break Interrupt Indicator.
0 : No break condition (default).
1 : The receiver received a break signal (RXD was ‘0’ for at least one
character frame time). In FIFO mode, only one character is loaded
into the RX FIFO.
3
2
1
0
LSR[3]
LSR[2]
LSR[1]
LSR[0]
Framing Error Indicator.
0 : No framing error (default).
1 : Framing error. It indicates that the received character did not have a
valid stop bit.
Parity Error Indicator.
0 : No parity error (default).
1 : Parity error. It indicates that the receive character did not have the
correct even or odd parity, as selected by the LCR[4]
Overrun Error Indicator.
0 : No overrun error (default).
1 : Overrun error. It indicates that the character in the RBR or RX FIFO
was not read by the CPU, thereby ignored the receiving character.
Receive Data Ready Indicator.
0 : No character in the RBR or RX FIFO.
1 : At least one character in the RBR or RX FIFO.
Rev. 00