IN16C1054
empty, line status, modem status, Xoff received, RTS# state transition from low to high, and
CTS# state transition from low to high. All interrupts are disabled if bit[7:0] are cleared.
Interrupt is enabled by setting appropriate bits. Table 9 shows IER bit settings.
Table 9: Interrupt Enable Register Description
Bit
Symbol Description
CTS# Interrupt Enable (Requires EFR[4] = 1).
7
IER[7]
IER[6]
IER[5]
IER[4]
IER[3]
IER[2]
IER[1]
IER[0]
0 : Disable the CTS# interrupt (default).
1 : Enable the CTS# interrupt.
6
5
4
3
2
1
0
RTS# Interrupt Enable (Requires EFR[4] = 1).
0 : Disable the RTS# interrupt (default).
1 : Enable the RTS# interrupt.
Xoff Interrupt Enable (Requires EFR[4] = 1).
0 : Disable the Xoff interrupt (default).
1 : Enable the Xoff interrupt.
Sleep Mode Enable (Requires EFR[4] = 1).
0 : Disable sleep mode (default).
1 : Enable sleep mode.
Modem Status Interrupt Enable
0 : Disable the modem status register interrupt (default).
1: Enable the modem status register interrupt.
Receive Line Status Interrupt Enable
0 : Disable the receive line status interrupt (default).
1: Enable the receive line status interrupt.
Transmit Holding Register Interrupt Enable
0 : Disable the THR interrupt (default).
1 : Enable the THR interrupt.
Receive Buffer Register Interrupt Enable
0 : Disable the RBR interrupt (default).
1 : Enable the RBR interrupt.
7.4 Interrupt Status Register (ISR, Page 0)
The UART provides multiple levels of prioritized interrupts to minimize software work load.
ISR provides the source of interrupt in a prioritized manner.
Rev. 00
IKSEMICON [ IK SEMICON CO., LTD ]
