IN16C1054
Addr.
A[2:0]
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page 3 Registers
0h
1h
PSR
ATR
1
0
1
0
0
0
1
0
0
Page
Select
Auto
Toggle
Mode
Bit 0
RXEN
Polarity
Select
RXEN
Enable
TXEN
Polarity
Select
TXEN
Enable
Auto
Toggle
Mode
Bit 1
2h
EFR
Auto-CTS# Auto-RTS#
Special
Character
Detect
Enable
Bit 5
Enhanced Software Software Software
Software
Flow
Control
Bit 0
Enable
Enable
Feature
Enable
Flow
Control
Bit 3
Flow
Control
Bit 2
Flow
Control
Bit 1
4h
5h
6h
7h
XON1
XON2
Bit 7
Bit 7
Bit 7
Bit 7
Bit 6
Bit 6
Bit 6
Bit 6
Bit 4
Bit 4
Bit 4
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 5
Bit 3
Bit 2
Bit 1
Bit 0
XOFF1
XOFF2
Bit 5
Bit 3
Bit 2
Bit 1
Bit 0
Bit 5
Bit 3
Bit 2
Bit 1
Bit 0
Page 4 Registers
1h
AFR
0
0
Global
Interrupt
Polarity
Select
0
Global
Interrupt
Enable
0
0
0
256-FIFO
Enable
2h
4h
5h
6h
7h
XRCR
TTR
0
0
0
0
0
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 7
Bit 7
Bit 7
Bit 7
Bit 6
Bit 6
Bit 6
Bit 6
Bit 5
Bit 4
Bit 4
Bit 4
Bit 4
Bit 3
Bit 3
Bit 3
Bit 3
Bit 2
Bit 2
Bit 2
Bit 2
RTR
FUR
FLR
Bit 5
Bit 5
Bit 5
7.1 Transmit Holding Register (THR, Page 0)
The transmitter section consists of the Transmit Holding Register (THR) and Transmit Shift
Register (TSR). The THR is actually a 64-byte FIFO or a 256-byte FIFO. The THR receives
data and shifts it into the TSR, where it is converted to serial data and moved out on the TX
terminal. If the FIFO is disabled, location zero of the FIFO is used to store the byte.
Characters are lost if overflow occurs.
7.2 Receive Buffer Register (RBR, Page 0)
The receiver section consists of the Receive Buffer Register (RBR) and Receive Shift
Register (RSR). The RBR is actually a 64-byte FIFO or a 256-byte FIFO. The RSR
receives serial data from external terminal. The serial data is converted to parallel data and
is transferred to the RBR. This receiver section is controlled by the line control register. If
the FIFO is disabled, location zero of the FIFO is used to store the characters. If overflow
occurs, characters are lost. The RBR also stores the error status bits associated with each
character.
7.3 Interrupt Enable Register (IER, Page 0)
IER enables each of the seven types of Interrupt, namely receive data ready, transmit
Rev. 00
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