IN16C1054
Table 8: Internal Registers Description
Addr. Reg.
A[2:0]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page 0 Registers
0h
0h
1h
THR
RBR
IER
Bit 7
Bit 7
Bit 6
Bit 6
Bit 5
Bit 4
Bit 4
Bit 3
Bit 3
Bit 2
Bit 2
Bit 1
Bit 1
Bit 0
Bit 0
Bit 5
0/Xoff
Interrupt
Enable
0/CTS#
Interrupt
Enable
0/RTS#
Interrupt
Enable
0/Sleep
Mode
Enable
Modem
Status
Interrupt
Enable
Receive
Line Status
Interrupt
Enable
THR
Empty
Interrupt Available
Enable
Receive
Data
Interrupt
Enable
2h
2h
ISR
FCR[0]/
256-TX
FIFO
Empty
RX
Trigger
Level
(MSB)
Divisor
Enable
FCR[0]/
256-RX
FIFO
Interrupt
Priority
Bit 5
Interrupt
Priority
Bit 4
Interrupt
Priority
Bit 3
Interrupt
Priority
Bit 2
Interrupt Interrupt
Priority
Bit 1
Priority
Bit 0
Full
FCR
RX
Trigger
Level
(LSB)
Set
TX Brake
0/TX
Trigger
Level
(MSB)
Set
0/TX
Trigger
Level
(LSB)
Parity
Type
Select
0/Loop
Back
DMA
Mode
Select
TX FIFO
Reset
RX FIFO
Reset
FIFO
Enable
3h
4h
LCR
Parity
Enable
Stop
Bits
Word
Length
Bit 1
Word
Length
Bit 0
Parity
MCR
Clock
Select
Page 2
Select/Xoff
Re-Transmit
Access
Enable
THR &
TSR
0/Xon
Any
OUT2/
INTx
Enable
OUT1/
Xoff Re-
Transmit
Enable
RTS#
DTR#
5h
LSR
RX FIFO
Data
THR
Empty
Receive
Break
Framing
Error
Parity
Error
Overrun
Error
Receive
Data
Error
Empty
Ready
∆CTS#
Bit 0
6h
7h
MSR
SCR
DCD#
Bit 7
RI#
DSR#
Bit 5
CTS#
Bit 4
∆DCD#
Bit 3
∆RI#
Bit 2
∆DSR#
Bit 1
Bit 6
Page 1 Registers
0h
1h
DLL
Bit 7
Bit 6
Bit 5
Bit 13
Bit 4
Bit 3
Bit 2
Bit 1
Bit 9
Bit 0
Bit 8
DLM
Bit 15
Bit 14
Bit 12
Bit 11
Bit 10
Page 2 Registers
1h
2h
GICR
GISR
0
0
0
0
0
0
0
0
Global
Interrupt
Mask
Global
Interrupt
Mask
Status
Bit 7
0
0
CH 3
Interrupt
Status
CH 2
Interrupt
Status
CH 1
Interrupt Interrupt
Status
CH 0
Status
5h
6h
7h
TCR
RCR
FSR
Bit 6
Bit 6
0
Bit 5
Bit 5
Bit 4
Bit 4
Bit 3
Bit 3
0
Bit 2
Bit 2
0
Bit 1
Bit 1
Bit 0
Bit 0
Bit 7
0
TX HW
Flow
TX SW
Flow
RX HW
Flow
RX SW
Flow
Control
Status
Control
Status
Control
Status
Control
Status
Table 8: Internal Registers Description…continued
Rev. 00
IKSEMICON [ IK SEMICON CO., LTD ]
