IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
ACELECTRICALCHARACTERISTICS(1)—SYNCHRONOUSTIMING
(Commercial: VCC = 2.5V ± 5%, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 5%, TA = -40°C to +85°C)
Commercial
Com’l & Ind’l
Commercial
IDT72T7285L4-4
IDT72T7295L4-4
IDT72T7285L5
IDT72T7295L5
IDT72T7285L6-7 IDT72T7285L10
IDT72T7295L6-7 IDT72T7295L10
IDT72T72105L4-4 IDT72T72105L5 IDT72T72105L6-7 IDT72T72105L10
IDT72T72115L4-4 IDT72T72115L5 IDT72T72115L6-7 IDT72T72115L10
Symbol
fC
Parameter
Clock Cycle Frequency (Synchronous)
DataAccessTime
Min.
—
0.6
4.44
2.0
2.0
1.2
0.5
1.2
0.5
1.2
0.5
1.2
0.5
—
100
45
Max.
225
3.4
—
—
—
—
—
—
—
—
—
—
—
10
Min.
—
0.6
5
Max.
200
3.6
—
—
—
—
—
—
—
—
—
—
—
10
Min.
—
0.6
6.7
2.8
2.8
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
—
100
45
Max.
150
3.8
—
—
—
—
—
—
—
—
—
—
—
10
Min.
Max.
100
4.5
—
—
—
—
—
—
—
—
—
—
—
10
Unit
MHz
ns
tA
0.6
10
4.5
4.5
3.0
0.5
3.0
0.5
3.0
0.5
3.0
0.5
—
100
45
45
15
5
tCLK
tCLKH
tCLKL
tDS
Clock Cycle Time
ns
Clock High Time
2.3
2.3
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
—
100
45
45
15
5
ns
Clock Low Time
ns
DataSetupTime
ns
tDH
DataHoldTime
ns
tENS
tENH
tLDS
EnableSetupTime
ns
EnableHoldTime
ns
LoadSetupTime
ns
tLDH
tWCSS
tWCSH
fS
LoadHoldTime
ns
WCSsetuptime
WCSholdtime
Clock Cycle Frequency (SCLK)
ns
ns
MHz
ns
tSCLK
tSCKH
tSCKL
tSDS
tSDH
tSENS
tSENH
tRS
Serial Clock Cycle
—
—
—
—
—
—
—
—
—
—
—
10
—
—
—
—
—
—
—
—
—
—
—
12
—
—
—
—
—
—
—
—
—
—
—
15
—
—
—
—
—
—
—
—
—
—
—
15
Serial Clock High
ns
Serial Clock Low
45
45
ns
SerialDataInSetup
15
15
ns
Serial Data In Hold
5
5
ns
SerialEnableSetup
5
5
5
5
ns
SerialEnableHold
ResetPulseWidth(2)
5
5
5
5
ns
30
30
15
4
30
30
15
4
ns
tRSS
tHRSS
tRSR
tRSF
tWFF
tREF
tPAFS
tPAES
ResetSetupTime
15
15
ns
HSTLResetSetupTime
ResetRecoveryTime
ResettoFlagandOutputTime
Write Clock to FF or IR
Read Clock to EF or OR
WriteClocktoSynchronousProgrammableAlmost-FullFlag
ReadClocktoSynchronousProgrammableAlmost-EmptyFlag
4
4
µs
ns
10
10
—
—
—
—
—
—
—
—
—
4
10
10
—
—
—
—
—
—
—
—
—
7
—
—
—
—
—
—
—
—
—
3.5
4
—
—
—
—
—
—
—
—
—
5
ns
3.4
3.4
3.4
3.4
3.8
3.4
3.4
3.4
—
—
3.6
3.6
3.6
3.6
4
3.8
3.8
3.8
3.8
4.3
3.8
3.8
3.8
—
—
4.5
4.5
4.5
4.5
5
ns
ns
ns
ns
tERCLK RCLK to Echo RCLK output
ns
tCLKEN
tRCSLZ
RCLK to Echo REN output
RCLK to Active from High-Z
3.6
3.6
3.6
—
—
4.5
4.5
4.5
—
—
ns
(3)
ns
(3)
tRCSHZ RCLK to High-Z
ns
tSKEW1 Skew time between RCLK and WCLK for EF/OR and FF/IR
tSKEW2 Skew time between RCLK and WCLK for PAE and PAF
ns
5
6
8
ns
NOTES:
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.
4. Industrial temperature range product for the 5ns speed grade is available as a standard device. All other speed grades are available by special order.
10
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
