IDT72605/IDT72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
COMMERCIAL TEMPERATURE RANGE
FUNCTIONAL DESCRIPTION
RESET
IDTs SyncBiFIFO is versatile for both multiprocessor and
Reset is accomplished whenever the Reset (RS) input is
peripheral applications. Data can be stored or retrieved from taken to a LOW state with CSA, ENA and ENB HIGH. During
two sources simultaneously. reset, both internal read and write pointers are set to the first
The SyncBiFIFO has registers on all inputs and outputs. location. A reset is required after power up before a write
Data is only transferred into the I/O registers on clock edges, operation can take place. The A→B and B→A FIFO Empty
hence the interfaces are synchronous. Two Dual-Port FIFO Flags (EFAB, EFBA) and Programmable Almost Empty Flags
memory arrays are contained in the SyncBiFIFO; one data (PAEAB, PAEBA) will be set to LOW after tRSF. The A→B and
buffer for each direction. Each port has its own independent B→AFIFOFullFlags(FFAB, FFBA)andProgrammableAlmost
clock. Data transfers to the I/O registers are gated by the Full Flags (PAFAB, PAFBA) will be set to HIGH after tRSF. After
enable signals. The transfer direction for each port is con- the reset, the offsets of the Almost-Empty Flags and Almost-
trolled independently by a read/write signal. Individual output Full Flags for the A→B and B→A FIFO offset default to 8.
enable signals control whether the SyncBiFIFO is driving the
data lines of a port or whether those data lines are in a high-
impedance state. The processor connected to Port A of the
PORT A INTERFACE
The SyncBiFIFO is straightforward to use in micro-pro-
BiFIFO can send or receive messages directly to the Port B
cessor-based systems because each port has a standard
device using the 18-bit bypass path.
microprocessor control set. Port A interfaces with micropro-
cessorthroughthethreeaddresspins(A2-A0)andaChipSelect
TheSyncBiFIFOcanbeusedinmultiplesof18-bits.Ina36-
to 36-bit configuration, two SyncBiFIFOs operate in parallel.
CSA pins. WhenCSA isasserted,A2,A1,A0 andR/WA areused
Both devices are programmed simultaneously, 18 data bits to
to select one of six internal resources (Table 1).
each device. This configuration can be extended to wider bus
With A2=0 and A1=0, A0 determines whether data can be
widths (54- to 54-bits, 72- to 72-bits, etc.) by adding more
read out of output register or be written into the FIFO (A0=0),
SyncBiFIFOs to the configuration. Figure 1 shows multiple
or the data can pass through the FIFO through the bypass
SyncBiFIFOs configured for multiprocessor communication.
path (A0=1).
The microprocessor or microcontroller connected to Port A
controls all operations of the SyncBiFIFO. Thus, all Port A
interface pins are inputs driven by the controlling processor.
Port B interfaces with a second processor. The Port B control
With A2=1, four programmable flags (two A→B FIFO pro-
grammable flags and two B→A FIFO programmable flags)
can be selected: the A→B FIFO Almost-Empty Flag Offset
(A1=0,A0=0),A→BFIFOAlmost-FullFlagOffset(A1=0,A0=1),
pins are inputs driven by the second processor.
B→AFIFOAlmost-EmptyFlagOffset(A1=1,A0=0),B→AFIFO
Almost-Full Flag Offset (A1=1, A0=1).
Port A is disabled when CSA is deasserted and data A is in
high-impedance state.
IDT
SYNCBIFIFO
DATA A
CLK
DATA B
CLK
CLK
A
B
CLK
CONTROL A CONTROL B
MICROPROCESSOR
A
MICROPROCESSOR
B
DATA
DATA
IDT
SYNCBIFIFO
CONTROL
LOGIC
CONTROL
LOGIC
ADDR, I/0
ADDR, I/0
DATA A
CLK
CONTROL A CONTROL B
DATA B
A
CLK
B
RAM A
RAM B
SYSTEM
CLOCK A
SYSTEM
CLOCK B
2704 drw 06
NOTES:
1. Upper SyncBiFIFO only is used in 18- to 18-bit configuration.
2. Control A Consists of R/WA, ENA, OEA, CSA, A2, A1, A0. Control B consists of R/WB, ENB, OEB.
Figure 1. 36- to 36-bit Processor Interface Configuration.
5.18
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IDT [ INTEGRATED DEVICE TECHNOLOGY ]
