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IDT72605L25J 参数 Datasheet PDF下载

IDT72605L25J图片预览
型号: IDT72605L25J
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS SyncBiFIFOO 256 ×18× 2和512 ×18× 2 [CMOS SyncBiFIFOO 256 x 18 x 2 and 512 x 18 x 2]
分类和应用: 先进先出芯片
文件页数/大小: 20 页 / 212 K
品牌: IDT [ INTEGRATED DEVICE TECHNOLOGY ]
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IDT72605/IDT72615 CMOS SyncBiFIFO  
256 x 18 x 2 and 512 x 18 x 2  
COMMERCIAL TEMPERATURE RANGE  
PIN DESCRIPTION  
Symbol  
Name  
I/O  
Description  
DA0-DA17 Data A  
I/O Data inputs & outputs for the 18-bit Port A bus.  
CSA  
Chip Select A  
I
I
Port A is accessed when CSA is LOW. Port A is inactive if CSA is HIGH.  
R/WA  
Read/Write A  
This pin controls the read or write direction of Port A. If R/WA is LOW, Data A input data is  
written into Port A. If R/WA is HIGH, Data A output data is read from Port A. In bypass mode,  
when R/WA is LOW, message is written into AB output register. If R/WA is HIGH, message  
is read from BA output register.  
CLKA  
ENA  
Clock A  
I
I
I
CLKA is typically a free running clock. Data is read or written into Port A on the rising edge of  
CLKA.  
Enable A  
When ENA is LOW, data can be read or written to Port A. When ENA is HIGH, no data  
transfers occur.  
OEA  
Output Enable A  
When R/WA is HIGH , Port A is an output bus and OEA controls the high-impedance state of  
DA0-DA17. If OEA is HIGH, Port A is in a high-impedance state. If OEA is LOW while CSA is  
LOW and R/WA is HIGH, Port A is in an active (low-impedance) state.  
A0, A1, A2 Addresses  
DB0-DB17 Data B  
I
When CSA is asserted, A0, A1, A2 and R/WA are used to select one of six internal resources.  
I/O Data inputs & outputs for the 18-bit Port B bus.  
R/WB  
Read/Write B  
I
This pin controls the read or write direction of Port B. If R/WB is LOW, Data B input data is  
written into Port B. If R/WB is HIGH, Data B output data is read from Port B. In bypass mode,  
when R/WB is LOW, message is written into BA output register. If R/WB is HIGH, message  
is read from AB output register.  
CLKB  
ENB  
Clock B  
I
I
I
Clock B is typically a free running clock. Data is read or written into Port B on the rising edge  
of CLKB.  
Enable B  
When ENB is LOW, data can be read or written to Port B. When ENB is HIGH, no data  
transfers occur.  
OEB  
Output Enable B  
When R/WB is HIGH , Port B is an output bus and OEB controls the high-impedance state of  
DB0-DB17. If OEB is HIGH, Port B is in a high-impedance state. If OEB is LOW while R/WB  
is HIGH, Port B is in an active (low-impedance) state.  
EFAB  
AB Empty Flag  
O
O
O
O
When EFAB is LOW, the AB FIFO is empty and further data reads from Port B are inhibited.  
When EFAB is HIGH, the FIFO is not empty. EFAB is synchronized to CLKB. In the bypass  
mode, EFAB HIGH indicates that data DA0-DA17 is available for passing through. After the  
data DB0-DB17 has been read, EFAB goes LOW.  
PAEAB  
PAFAB  
FFAB  
AB  
Programmable  
Almost-Empty Flag  
When PAEAB is LOW, the AB FIFO is almost empty. An almost empty FIFO contains less  
than or equal to the offset programmed into PAEAB Register. When PAEAB is HIGH, the  
AB FIFO contains more than offset in PAEAB Register. The default offset value for PAEAB  
Register is 8. PAEAB is synchronized to CLKB.  
AB  
Programmable  
Almost-Full Flag  
When PAFAB is LOW, the AB FIFO is almost full. An almost full FIFO contains greater than  
the FIFO depth minus the offset programmed into PAFAB Register. When PAFAB is HIGH,  
the AB FIFO contains less than or equal to the depth minus the offset in PAFAB Register.  
The default offset value for PAFAB Register is 8. PAFAB is synchronized to CLKA.  
AB Full Flag  
When FFAB is LOW, the AB FIFO is full and further data writes into Port A are inhibited.  
When FFAB is HIGH, the FIFO is not full. FFAB is synchronized to CLKA. In bypass mode,  
FFAB tells Port A that a message is waiting in Port B’s output register. If FFAB is LOW, a  
bypass message is in the register. If FFAB is HIGH, Port B has read the message and another  
message can be written into Port A.  
EFBA  
BA Empty Flag  
O
O
O
When EFBA is LOW, the BA FIFO is empty and further data reads from Port A are inhibited.  
When EFBA is HIGH, the FIFO is not empty. EFBA is synchronized to CLKA. In the bypass  
mode, EFBA HIGH indicates that data DB0-DB17 is available for passing through. After the  
data DA0-DA17 has been read, EFBA goes LOW on the following cycle.  
PAEBA  
PAFBA  
BA  
Programmable  
Almost-Empty Flag  
When PAEBA is LOW, the BA FIFO is almost empty. An almost empty FIFO contains less  
than or equal to the offset programmed into PAEBA Register. When PAEBA is HIGH, the  
BA FIFO contains more than offset in PAEBA Register. The default offset value for PAEBA  
Register is 8. PAEBA is synchronized to CLKA.  
BA  
Programmable  
Almost-Full Flag  
When PAFBA is LOW, the BA FIFO is almost full. An almost full FIFO contains greater than  
the FIFO depth minus the offset programmed into PAFBA Register. When PAFBA is HIGH,  
the BA FIFO contains less than or equal to the depth minus the offset in PAFBA Register.  
The default offset value for PAFBA Register is 8. PAFBA is synchronized to CLKB.  
2704 tbl 01  
5.18  
4