IDT72605/IDT72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
COMMERCIAL TEMPERATURE RANGE
+5V
AC TEST CONDITIONS
In Pulse Levels
GND to 3.0V
3ns
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
1.1KΩ
1.5V
1.5V
D.U.T.
See Figure 2
2704 tbl 07
680Ω
30pF*
2704 drw 05
or equivalent circuit
Figure 2. Output Load
* Includes jig and scope capacitances.
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V±10%, TA = 0°C to +70°C)
Commercial
72615L20
72605L20
72615L25
72605L25
72615L35
72605L35
72615L50
72605L50
Symbol
Parameter
Clock frequency
Min.
Max. Min. Max. Min. Max. Min.
Max. Unit
Timing Figures
fCLK
—
50
—
—
—
—
—
—
27
10
—
—
25
10
10
25
15
15
—
3
40
—
—
—
—
—
—
28
15
—
—
35
14
14
35
21
21
—
3
28
—
—
—
—
—
—
35
21
—
—
50
20
20
50
30
30
—
3
20 MHz
—
tCLK
tCLKH
tCLKL
tRS
Clock cycle time
20
8
—
—
—
—
—
—
50
25
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
4,5,6,7
Clock HIGH time
4,5,6,7,12,13,14,15
Clock LOW time
8
4,5,6,7,12,13,14,15
Reset pulse width
20
12
12
—
3
3
tRSS
tRSR
tRSF
tA
Reset set-up time
3
Reset recovery time
Reset to flags in intial state
Data access time
3
3
5,7,8,9,10,11
tCS
Control signal set-up time(1)
6
6
8
10
4,5,6,7,8,9,10,11,
12, 13,14,15
tCH
Control signal hold time(1)
1
—
1
—
1
—
1
—
ns
4,5,6,7,10,11,12,
13, 14,15
tDS
tDH
tOE
Data set-up time
Data hold time
6
1
3
—
—
10
6
1
3
—
—
13
8
1
3
—
—
20
10
1
—
—
28
ns
ns
ns
4,6,8,9,10,11
4,6
Output Enable LOW to
output data valid(2)
3
5,7,8,9,10,11
tOLZ
tOHZ
Output Enable LOW to data
bus at Low-Z(2)
0
3
—
0
3
—
0
3
—
0
3
—
ns
ns
5,7,8,9,10,11
5,7,10,11
Output Enable HIGH to data
bus at High-Z(2)
10
13
20
28
tFF
tEF
Clock to Full Flag time
—
—
—
10
10
12
—
—
—
15
15
15
—
—
—
21
21
21
—
—
—
30
30
30
ns
ns
ns
4,6,10,11
5,7,8,9,10,11
12,14
Clock to Empty Flag time
tPAE
Clock to Programmable
Almost Empty Flag time
tPAF
tSKEW1
tSKEW2
NOTES:
Clock to Programmable
Almost Full Flag time
—
10
17
12
—
—
—
12
19
15
—
—
—
17
25
21
—
—
—
20
34
30
—
—
ns
ns
ns
13,15
Skew between CLKA & CLKB
for Empty/Full Flags(2)
4,5,6,7,8,9,10,11
4, 7,12,13,14,15
Skew between CLKA & CLKB
for Programmable Flags(2)
2704 tbl 08
1. Control signals refer to CSA, R/WA, ENA, A2, A1, A0, R/WB, ENB.
2. Minimum values are guaranteed by design.
5.18
6
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
