IDT72605/IDT72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
COMMERCIAL TEMPERATURE RANGE
inputregisterandtheFIFOmemory. IfR/WB isHIGHandOEB
isLOW, datacomesoutofbusandisreadfromoutputregister
into three-state buffer. In bypass mode, if R/WB is LOW,
bypass messages are transferred into B→A output register. If
R/WA is HIGH, bypass messages are transferred into A→B
outputregister. Refertopindescriptionsformoreinformation.
Data B
R/
B
W
B
EN
B
OE
I/O
Port B Operation
0
0
0
I
Data B is written on CLKB ↑. This write cycle immediately following output low-
impedance cycle is prohibited. Note that even though OEB = 0, a LOW logic level on
R/WB, once qualified by a rising edge on CLKB, will put Data B into a high-impedance
state.
0
0
1
0
1
0
1
X
0
I
I
Data B is written on CLKB ↑.
Data B is ignored
O
Data is read(1) from RAM array to output register on CLKB ≠, Data B is LOW
impedance
1
0
1
O
Data is read(1) from RAM array to output register on CLKB ≠, Data B is HIGH
impedance
1
1
1
1
0
1
O
O
Output register does not change(2), Data B is low-impedance
Output register does not change(2), Data B is high-impedance
2704 tbl 13
NOTES:
1. When A2A1A0 = 000 or 1XX, the next A→B FIFO value is read out of the output register and the read pointer advances. If A2A1A0 = 001, the bypass
path is selected and bypass data is read from the Port B output register.
2. Regardless of the condition of A2A1A0, the data in the Port B output register does not change and the A→B read pointer does not advance.
Table 5. Port B Operation Control Signals.
5.18
10
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
