IDT72605/IDT72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
COMMERCIAL TEMPERATURE RANGE
PROGRAMMABLE FLAGS
A
A2
0
A1
0
A0
0
Read
Write
CS
0
0
0
B→A FIFO A→B FIFO
TheIDTSyncBiFIFOhaseightflags:four flagsforA→BFIFO
(EFAB, PAEAB, PAFAB, FFAB), and four flags for B→A FIFO
(EFBA, PAEBA, PAFBA, FFBA). The Empty and Full flags are
fixed, while the Almost Empty and Almost Full offsets can be
set to any depth through the Flag Offset Registers (see Table
3). The flags are asserted at the depths shown in the Flag
Truth Table (Table 4). After reset, the programmable flag
offsets are set to 8. This means the Almost Empty flags are
asserted at Empty +8 words deep, and the Almost Full flags
are asserted at Full -8 words deep.
The PAEAB is synchronized to CLKB, while PAEAB is syn-
chronizedtoCLKA;andPAEBA issynchronizedtoCLKA, while
PAEBA is synchronized toCLKB. If the minimum time (tSKEW2)
between a rising CLKB and a rising CLKA is met, the flag will
change state on the current clock; otherwise, the flag may not
change state until the next clock rising edge. For the specific
flag timings, refer to Figures 12-15.
0
0
1
18-bit Bypass Path
1
0
0
A→B FIFO Almost-Empty
Flag Offset
0
0
0
1
1
1
1
X
0
1
1
X
1
0
1
X
A→B FIFO Almost-Full
Flag Offset
B→A FIFO Almost-Empty
Flag Offset
B→A FIFO Almost-Full
Flag Offset
Port A Disabled
2704 tbl 10
Table 2. Accessing Port A Resources Using
A, A2, A1, and A0.
CS
PORT A CONTROL SIGNALS
The Port A control signals pins dictate the various opera-
tions shown in Table 2. Port A is accessed whenCSA is LOW,
and is inactive if CSA is HIGH. R/WA and ENA lines determine
whenDataAcanbewrittenorread. IfR/WA andENAareLOW,
PORT B CONTROL SIGNALS
ThePortBcontrolsignalpinsdictatethevariousoperations
dataiswrittenintoinputregisterontheLOW-to-HIGHtransition shown in Table 5. Port B is independent of CSA. R/WB and
of CLKA. If R/WA is HIGH and OEA is LOW, data comes out ENB lines determine when Data can be written or read in Port
of bus and is read from output register into three-state buffer. B. IfR/WB andENB areLOW, dataiswrittenintoinputregister,
Refer to pin descriptions for more information.
and on LOW-to-HIGH transition of CLKB data is written into
17
X
16
X
15
X
14
X
13
X
12
X
11
X
10
X
9
8
8
8
8
7
6
5
4
3
2
1
0
0
0
PAEAB Register
PAFAB Register
PAEBA Register
X
A→B FIFO Almost-Empty Flag Offset
17
X
16
X
15
X
14
X
13
X
12
X
11
X
10
X
9
7
7
6
5
4
3
2
1
1
X
A→B FIFO Almost-Full Flag Offset
17
X
16
X
15
X
14
X
13
X
12
X
11
X
10
X
9
6
5
4
3
2
X
B→A FIFO Almost-Empty Flag Offset
17
X
16
X
15
X
14
X
13
X
12
X
11
X
10
X
9
7
6
5
4
3
2
1
0
PAFBA Register
X
B→A FIFO Almost-Full Flag Offset
2704 tbl 11
NOTE:
1. Bit 8 must be set to 0 for the IDT72605 (256 x 18) Synchronous BiFIFO.
Table 3. Flag Offset Register Format.
Number of Words
in FIFO
From
To
EF
PAE
LOW
LOW
HIGH
HIGH
HIGH
PAF
HIGH
HIGH
HIGH
LOW
LOW
FF
0
0
LOW
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
1
n
D-(m+1)
D-1
n+1
D-m
D
D
NOTES:
2704 tbl 12
n = Programmable Empty Offset (PAEAB Register or PAEBA Register)
m = Programmable Full Offset (PAFAB Register or PAFBA Register)
D = FIFO Depth (IDT72605 = 256 words, IDT72615= 512 words)
Table 4. Internal Flag Truth Table.
5.18
9
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
