CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
IDT72605
IDT72615
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• Two independent FIFO memories for fully bidirectional
data transfers
• 256 x 18 x 2 organization (IDT 72605)
• 512 x 18 x 2 organization (IDT 72615)
• Synchronous interface for fast (20ns) read and write
cycle times
• Each data port has an independent clock and read/write
control
• Output enable is provided on each port as a three-state
control of the data bus
• Built-in bypass path for direct data transfer between two
ports
• Two fixed flags, Empty and Full, for both the A-to-B and
the B-to-A FIFO
• Programmable flag offset can be set to any depth in the
FIFO
The IDT72605 and IDT72615 are very high-speed, low-
power bidirectional First-In, First-Out (FIFO) memories, with
synchronous interface for fast read and write cycle times. The
SyncBiFIFO
is a data buffer that can store or retrieve
information from two sources simultaneously. Two Dual-Port
FIFO memory arrays are contained in the SyncBiFIFO; one
data buffer for each direction.
The SyncBiFIFO has registers on all inputs and outputs.
Data is only transferred into the I/O registers on clock edges,
hence the interfaces are synchronous. Each Port has its own
independent clock. Data transfers to the I/O registers are
gated by the enable signals. The transfer direction for each
portiscontrolledindependentlybyaread/writesignal. Individ-
ual output enable signals control whether the SyncBiFIFO is
driving the data lines of a port or whether those data lines are
in a high-impedance state.
• The synchronous BiFIFO is packaged in a 64-pin TQFP
(Thin Quad Flatpack), 68-pin PGA and 68-pin PLCC
• Industrial temperature range (-40oC to +85oC) is avail-
able, tested to military electrical specifications
Bypass control allows data to be directly transferred from
input to output register in either direction.
The SyncBiFIFO has eight flags. The flag pins are full,
empty, almost-full, and almost-empty for both FIFO memo-
ries. The offset depths of the almost-full and almost-empty
flags can be programmed to any location.
The SyncBiFIFO is fabricated using IDT’s high-speed,
submicron CMOS technology.
FUNCTIONAL BLOCK DIAGRAM
DA0-DA17
ENA
R/WA
HIGH
Z
CONTROL
OEA
INPUT REGISTER
OUTPUT REGISTER
MUX
CLKA
RESET
LOGIC
CSA
A2
RS
µP
A1
INTERFACE
A0
EFAB
PAEAB
PAFAB
FFAB
MEMORY
ARRAY
512 x 18
256 x 18
MEMORY
ARRAY
512 x 18
256 x 18
EFBA
FLAG
LOGIC
FLAG
LOGIC
PAEBA
PAFBA
FFBA
3
7
POWER
SUPPLY
MUX
VCC
GND
OUTPUT REGISTER
INPUT REGISTER
CLKB
HIGH
Z
CONTROL
OEB
R/WB
ENB
2704 drw 01
BYPB
DB0-DB17
SyncBiFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGES
DECEMBER 1996
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
1996 Integrated Device Technology, Inc.
DSC-2704/5
5.18
1
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
