IDT72605/IDT72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
COMMERCIAL TEMPERATURE RANGE
t
CLKH
tCLKL
CLK
B
B
t
CS
tCH
EN
(R/W
A = 0)
WRITE
n words in FIFO
n+1 words in FIFO
PAEBA
(1)
tSKEW2
tPAE
tPAE
(2)
CLK
EN
A
A
t
CS
tCH
2704 drw 18
(R/WA = 1)
READ
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for PAEBA to change during that clock cycle. If the time between the
rising edge of CLKB and the rising edge of CLKA is less than tSKEW2, then PAEBA may not go HIGH until the next CLKA rising edge.
2. If a read is performed on this rising edge of the read clock, there will be Empty + (n - 1) words in the FIFO when PAE goes LOW.
Figure 14. B→A Programmable Almost-Empty Flag Timing
tCLKH
tCLKL
tCS
(2)
CLKB
tCH
ENB
(R/WA = 0)
WRITE
Full - (m+1) words in FIFO
Full - m words in FIFO
PAFBA
CLKA
(1)
tPAF
tSKEW2
tPAF
tCS
tCH
ENA
(R/WA = 1)
READ
2704 drw 19
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for PAFBA to change during that clock cycle. If the time between the
rising edge of CLKB and the rising edge of CLKA is less than tSKEW2, then PAFBA may not go HIGH until the next CLKA rising edge.
2. If a write is performed on this rising edge of the write clock, there will be Full - (m + 1) words in the FIFO when PAF goes LOW.
Figure 15. B→A Programmable Almost-Full Flag Timing
5.18
19
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
