IDT72605/IDT72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
COMMERCIAL TEMPERATURE RANGE
CLKA
A0, A1, A2 ,
R/WA
tCS
A2, A1 , A0 , = 001
tCH
CSA
tCS
tCH
ENA
tFF
tFF
tFF
BYPASS FLAG
FIFO FLAG
FFAB
tDS
DA0-DA17
DATA INPUT
tSKEW1
tSKEW1
tSKEW1
CLKB
R/WB
ENB
tCS
tEF
tEF
tEF
FIFO FLAG
BYPASS FLAG
FIFO FLAG
EFAB
BYPB
tA
DB0-DB17
DATA OUTPUT
tOLZ
tOE
tOHZ
OEB
2704 drw 14
NOTES:
1. When CSA is brought HIGH, A→B Bypass mode will switch to FIFO mode on the following CLKA LOW-to-HIGH transition.
2. After the bypass operation is completed, the BYPB goes from LOW-to-HIGH; this will reset all bypass flags. The bypass path becomes available for
the next bypass operation.
3. When A-side changed from bypass mode into FIFO mode, B-side only has one cycle to read the bypass data. On the next cycle, B-side will be
forced back to FIFO mode.
Figure 10. A→B Bypass Timing
5.18
16
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
