IDT72605/IDT72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
COMMERCIAL TEMPERATURE RANGE
CLKA
A0, A1, A2 ,
R/WA
tCS
CSA , EN
A
tDS
DA0-DA17
D0 (First valid write)
D1
D2
D3
tFRL
(1)
tSKEW1
CLKB
R/WB
ENB
tCS
tEF
EFAB
tA
tA
DB0-DB17
D0
D1
tOLZ
tOE
OEB
2704 drw 12
NOTE:
1. When tSKEW1 ≥ minimum specification, tFRL(Max.) = tCLK + tSKEW1
tSKEW1 < minimum specification, tFRL(Max.) = 2tCLK + tSKEW1 or tCLK + tSKEW1
The Latency Timing applies only at the Empty Boundary (EF = LOW).
Figure 8. A→B First Data Word Latency after Reset for Simultaneous Read and Write
5.18
14