IDT72605/IDT72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
COMMERCIAL TEMPERATURE RANGE
tCLKH
tCLKL
tCS
CLKA
tCH
ENA
(R/WA = 0)
n+1 words in FIFO
WRITE
n words in FIFO
PAEAB
CLKB
(1)
tSKEW2
tPAE
tPAE
(2)
tCS
tCH
ENA
(R/WB = 1)
2704 drw 16
READ
NOTES:
1. tSKEW2 the minimum time between a rising CLKA edge and a rising CLKB edge for PAEAB to change during that clock cycle. If the time between the
rising edge of CLKA and the rising edge of CLKB is less than tSKEW, then PAEAB may not go HIGH until the next CLKB rising edge.
2. If a read is performed on this rising edge of the read clock, there will be Empty + (n + 1) words in the FIFO when PAE goes LOW.
Figure 12. A→B Programmable Almost-Empty Flag Timing
tCLKH
tCLKL
tCS
(2)
CLKA
tCH
ENA
(R/W A = 0)
WRITE
Full - (m+1) words in FIFO
Full - m words in FIFO
PAFAB
CLKB
tPAF
tPAF
tCH
tCS
ENB
(R/W B = 1)
2704 drw 17
READ
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for PAFAB to change during that clock cycle. If the time between the
rising edge of CLKB and the rising edge of CLKA is less than tSKEW2, then PAFAB may not go HIGH until the next CLKA rising edge.
2. If a write is performed on this rising edge of the write clock, there will be Full - (m + 1) words in the FIFO when PAF goes LOW.
Figure 13. A→B Programmable Almost-Full Flag Timing
5.18
18
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
