IDT72605/IDT72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
COMMERCIAL TEMPERATURE RANGE
CLK
R/W
EN
B
B
B
tCS
tCH
FIFO FLAG
tFF
t
FF
t
FF
t
FF
FFBA
BYPASS FLAG
BYP
B
t
DS
DATA INPUT
D
B0-DB17
tSKEW1
tSKEW1
tSKEW1
tSKEW1
CLK
A
tCS
tCS
A
2
, A1 , A0 , = 001
A0
, A
1
, A2,
tCS
CS
A
A
A
R/W
EN
tCS
t
EF
tEF
tEF
tEF
FIFO FLAG
BYPASS FLAG
FIFO FLAG
EFBA
tA
DATA OUTPUT
D
A0-DA17
tOLZ
t
OE
tOHZ
OE
A
2704 drw 15
NOTES:
1. When CSA is brought HIGH, A→B Bypass mode will switch to FIFO mode on the following CLKA going LOW-to-HIGH.
2. After the bypass operation is completed, the BYPB goes from LOW-to-HIGH; this will reset all bypass flags. The bypass path becomes available for
the next bypass operation.
3. When A-side changed from bypass mode into FIFO mode, B-side only has one cycle to read the bypass data. On the next cycle, B-side will be
forced back to FIFO mode.
Figure 11. B→A Bypass Timing
5.18
17
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
