IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of BUSY Arbitration Controlled by CE Timing(1)
ADDR
ADDRESSES MATCH
"A" and "B"
CE"B"
(2)
tAPS
CE"A"
t
BAC
tBDC
BUSY"A"
2692 drw 13
Timing Waveform of BUSY Arbitration Controlled
by Address Match Timing(1)
tRC or tWC
ADDR"A"
ADDR"B"
BUSY"B"
ADDRESSES MATCH
ADDRESSES DO NOT MATCH
(2)
APS
t
tBAA
tBDA
2692 drw 14
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (7132 only).
Truth Tables
Table I. Non-Contention Read/Write Control(4)
Left or Right Port(1)
R/W
X
D
0-7
Function
Port Disabled and in Power-Down Mode, ISB2 or ISB4
CE = CE = VIH, Power-Down Mode, ISB1 or ISB3
CE
H
H
L
OE
X
Z
Z
X
X
R
L
L
X
DATAIN
DATAOUT
Z
Data on Port Written into Memory(2)
Data in Memory Output on Port(3)
High Impedance Outputs
H
L
L
X
L
H
2692 tbl 12
NOTES:
1. A0L - A10L ≠ A0R - A10R
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see tWDD and tDDD timing.
4. 'H' = VIH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = HIGH IMPEDANCE
13
6.42
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
