IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle No. 1, Either Side(1)
tRC
ADDRESS
tAA
tOH
tOH
DATAOUT
PREVIOUS DATA VALID
DATA VALID
BUSYOUT
2692 drw 07
(2,3)
BDDH
t
Timing Waveform of Read Cycle No. 2, Either Side(1)
tACE
CE
OE
(3)
(5)
tHZ
tAOE
(5)
HZ
(4)
t
tLZ
VALID DATA
DATAOUT
(4)
LZ
(3)
t
tPD
tPU
ICC
CURRENT
50%
50%
ISS
2692 drw 08
NOTES:
1. R/W = VIH, CE = VIL, and is OE = VIL. Address is valid prior to the coincidental with CE transition LOW.
2. tBDD delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read operations, BUSY has
no relationship to valid output data.
3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
4. Timing depends on which signal is asserted last, OE or CE.
5. Timing depends on which signal is de-asserted first, OE or CE.
8
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
