IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, (R/W Controlled Timing)(1,5,8)
tWC
ADDRESS
OE
(7)
HZ
t
tAW
CE
(6)
AS
(3)
tWR
(2)
WP
(7)
HZ
t
t
t
R/W
(7)
WZ
t
OW
t
(4)
(4)
OUT
DATA
tDW
t
DH
IN
DATA
2692 drw 09
Timing Waveform of Write Cycle No. 2, (CE Controlled Timing)(1,5)
t
WC
ADDRESS
CE
t
AW
(6)
(2)
tEW
(3)
WR
t
tAS
R/W
tDW
tDH
IN
DATA
2692 drw 10
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of CE = VIL and R/W = VIL.
3. tWR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle.
4. During this period, the l/O pins are in the output state and input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. This parameter is determined be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the
bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
10
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
