IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(7,8)
7132X20(1)
7142X20(1)
Com'l Only
7132X25(2)
7132X35
7142X35
Com'l &
Military
7142X25(2)
Com'l, Ind
& Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY Timing (For Master IDT7132 Only)
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
BAA
BDA
BAC
BDC
WDD
WH
DDD
APS
BDD
20
20
20
20
20
20
20
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address
BUSY Disable Time from Address
t
t
BUSY Access Time from Chip Enable
BUSY Disable Time from Chip Enable
Write Pulse to Data Delay(2)
t
t
50
50
60
t
Write Hold After BUSY(6)
12
15
20
____
____
____
t
Write Data Valid to Read Data Delay(2)
Arbitration Priority Set-up Time(3)
BUSY Disable to Valid Data(4)
35
35
35
____
____
____
____
____
____
t
5
5
5
____
____
____
t
25
35
35
BUSY Timing (For Slave IDT7142 Only)
____
____
____
____
____
____
t
WB
WH
WDD
DDD
Write to BUSY Input(5)
0
0
0
ns
ns
ns
t
Write Hold After BUSY(6)
12
15
20
____
____
____
t
Write Pulse to Data Delay(2)
Write Data Valid to Read Data Delay(2)
40
30
50
35
60
35
____
____
____
t
ns
2692 tbl 11a
7132X55
7132X100
7142X55
Com'l &
Military
7142X100
Com'l &
Military
Symbol
BUSY Timing (For Master IDT7132 Only)
Parameter
Min.
Max.
Min.
Max.
Unit
____
____
____
____
____
____
____
____
____
____
t
BAA
BDA
BAC
BDC
WDD
WH
DDD
APS
BDD
30
30
30
30
50
50
50
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address
BUSY Disable Time from Address
BUSY Access Time from Chip Enable
BUSY Disable Time from Chip Enable
Write Pulse to Data Delay(2)
t
t
t
t
80
120
(6)
____
____
t
Write Hold After BUSY
20
20
t
Write Data Valid to Read Data Delay(2)
Arbitration Priority Set-up Time(3)
BUSY Disable to Valid Data(4)
55
100
____
____
____
____
t
5
5
____
____
t
50
65
BUSY Timing (For Slave IDT7142 Only)
Write to BUSY Input(5)
____
____
____
____
t
WB
WH
WDD
DDD
0
0
ns
ns
ns
(6)
t
Write Hold After BUSY
20
20
Write Pulse to Data Delay(2)
Write Data Valid to Read Data Delay(2)
80
55
120
100
____
____
t
____
____
t
ns
2692 tbl 11b
NOTES:
1. PLCC package only.
2. Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port -to-Port Read and BUSY.”
3. To ensure that the earlier of the two ports wins.
4. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
5. To ensure that a write cycle is inhibited on port "B" during contention on port "A".
6. To ensure that a write cycle is completed on port "B" after contention on port "A".
7. 'X' in part numbers indicates power rating (SA or LA).
8. Industrial temperature: for specific speeds, packages and powers contact your sales office.
11
6.42
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