ICS1894-40
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
MII Management Interface Timing
The table below lists the significant time periods for the MII Management Interface timing (which consists of timings
of signals on the MDC and MDIO pins). The MII Management Interface Timing Diagram figure shows the timing
diagram for the time periods.
Time
Parameter
Conditions Min. Typ. Max. Units
Period
t1
t2
t3
t4
t5
t6
MDC Minimum High Time
–
–
–
–
–
–
160
160
400
0
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
MDC Minimum Low Time
MDC Period
–
MDC Rise Time to MDIO Valid
MDIO Setup Time to MDC
MDIO Hold Time after MDC
300
–
10
10
–
MII Management Interface Timing Diagram
MDC
t1
t2
t3
t4
MDIO
(Output)
MDC
MDIO
(Input)
t5
t6
IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
37
ICS1894-40
REV G 060110
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
