ICS1894-40
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
Timing for Transmit Clock (TXCLK) Pin
The table below lists the significant time periods for signals on the Transmit Clock (TXCLK) pin. The Transmit Clock
Timing Diagram figure shows the timing diagram for the time periods.
Time
Parameter
Conditions
Min. Typ. Max. Units
Period
t1
TXCLK Duty Cycle
TXCLK Period
–
35
–
50
40
65
–
%
ns
ns
t2a
t2b
100M MII (100Base-TX)
10M MII (10Base-T)
TXCLK Period
–
400
–
Transmit Clock Timing Diagram
t1
TXCLK
t2x
Timing for Receive Clock (RXCLK) Pin
The table below lists the significant time periods for signals on the Receive Clock (RXCLK) pin. The Receive Clock
Timing Diagram figure shows the timing diagram for the time periods.
Time
Parameter
Conditions
Min. Typ. Max. Units
Period
t1
RXCLK Duty Cycle
RXCLK Period
–
35
–
50
40
65
–
%
ns
ns
t2a
t2b
100M MII (100Base-TX)
10M MII (10Base-T)
RXCLK Period
–
400
–
Receive Clock Timing Diagram
t1
RXCLK
t2
IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
34
ICS1894-40
REV G 060110
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
