ICS1894-40
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
10M MII Synchronous Transmit Timing Diagram
TXCLK
TXD[3:0]
TXEN
TXER
t1
t2
100M/MII Media Independent Interface: Synchronous Receive Timing
The table below lists the significant time periods for the MII/100M Stream Interface synchronous receive timing. The
time periods consist of timings of signals on the following pins:
• RXCLK
• RXD[3:0]
• RXDV
• RXER
The MII Interface: Synchronous Receive Timing figure shows the timing diagram for the time periods.
Time
Parameter
Min. Typ. Max. Units
Period
t1
t2
RXD[3:0], RXDV, and RXER Setup to RXCLK Rise
RXD[3:0], RXDV, and RXER Hold after RXCLK Rise
10.0
10.0
–
–
–
–
ns
ns
MII Interface: Synchronous Receive Timing
RXCLK
RXD[3:0]
RXDV
RXER
t1
t2
IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
36
ICS1894-40
REV G 060110
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
