ICS1893AF Data Sheet - Release
Chapter 10 DC and AC Operating Conditions
10.5.16 Reset: Hardware Reset and Power-Down
Table 10-23 lists the significant time periods for the hardware reset and power-down reset. The time
periods consist of timings of signals on the following pins:
• REF_IN
• RESETn
• TXCLK
Figure 10-17 shows the timing diagram for the time periods.
Table 10-23. Hardware Reset and Power-Down Timing
Time
Period
Parameter
Condi-
tions
Min. Typ. Max. Units
t1
t2
t3
RESETn Active to Device Isolation and Initialization
Minimum RESETn Pulse Width
–
–
–
–
500
–
60
40
35
–
–
ns
ns
RESETn Released to TXCLK Valid
500
ms
Figure 10-17. Hardware Reset and Power-Down Timing Diagram
REF_IN
RESETn
t1
t2
t3
TXCLK Valid
Power
Consumption
(AC only)
ICS1893AF, Rev. D 10/26/04
October, 2004
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
129
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
