ICS1892
10Base-T/100Base-TX Integrated PHYceiver™
TSD
Chapter 8 Management Register Set
ICS1892 Data Sheet
8.3 Register 1: Status Register
Table 8-6 lists the bits for the Status Register, an interface between the ICS1892 and the STA that has 16
bits of data. There are two types of status bits: some report the capabilities of the ICS1892, and some
indicate the state of signals used to monitor internal circuits.
The STA accesses the Status Register using the Serial Management Interface. During a reset, the
ICS1892 initializes the Status Register bits to pre-defined, default values.
Note: For an explanation of acronyms used in Table 8-5, see Chapter 1, “Abbreviations and Acronyms”.
Table 8-6. Status Register (Register 1 [0x01])
Bit
Definition
When Bit = 0
When Bit = 1
Ac-
cess
SF
De- Hex
fault
1.15 100Base-T4
Always 0. (Not supported.) N/A
RO
CW
CW
CW
CW
CW
CW
CW
CW
RO
–
–
–
–
–
–
–
–
–
–
0
1
7
8
0
1.14 100Base-TX full duplex Mode not supported
1.13 100Base-TX half duplex Mode not supported
Mode supported
Mode supported
Mode supported
Mode supported
N/A
1
1.12 10Base-T full duplex
1.11 10Base-T half duplex
1.10 IEEE reserved
1.9 IEEE reserved
Mode not supported
Mode not supported
Always 0
1
1
0†
0†
0†
0†
0
Always 0
N/A
1.8 IEEE reserved
Always 0
N/A
1.7 IEEE reserved
Always 0
N/A
1.6 MF Preamble
suppression
PHY requires MF
Preambles
PHY does not require
MF Preambles
1.5 Auto-Negotiation
complete
Auto-Negotiation is in
process, if enabled
Auto-Negotiation is
completed
RO
LH
0
1.4 Remote fault
No remote Fault Detected Remote fault detected
RO
RO
LH
–
0
1
1.3 Auto-Negotiation ability N/A
Always 1: PHY has
9
Auto-Negotiation ability
1.2 Link status
Link is invalid/down
Link is valid/established
RO
RO
LL
0
0
1.1 Jabber detect
No jabber condition
Jabber condition
detected
LH
1.0 Extended capability
N/A
Always 1: PHY has
extended capabilities
RO
–
1
† As per the IEEE Std 802.3u, during any write operation to any bit in this register, the STA must write the default value
to all Reserved bits.
8.3.1 100Base-T4 (bit 1.15)
The STA reads this bit to learn if the ICS1892 can support 100Base-T4 operations. Bit 1.15 of the ICS1892
is permanently set to logic zero, which informs an STA that the ICS1892 cannot support 100Base-T4
operations.
ICS1892, Rev. D, 2/26/01
February 26, 2001
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
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IDT™ / ICS™ 10Base-T/100Base-TX Integrated PHYceiver™
ICS1892
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