ICS1892
10Base-T/100Base-TX Integrated PHYceiver™
TSD
Chapter 8 Management Register Set
ICS1892 Data Sheet
8.3.6 IEEE Reserved Bits (bits 1.10:7)
The IEEE reserves these bits for future use. When an STA:
• Reads a reserved bit, the ICS1892 returns a logic zero.
• Writes a reserved bit, the STA must use the default value specified in this data sheet.
Both the ISO/IEC standard and the ICS1892 reserve the use of some Management Register bits. ICS uses
some of these reserved bits to invoke ICS1892 test functions. To ensure proper operation of the ICS1892,
an STA must maintain the default value of these bits. Therefore, ICS recommends that an STA write the
default value to all reserved bits during all Management Register write operations.
Reserved bits 1.10:7 are Command Override Write (CW) bits. When bit 16.15, the Command Register
Override bit is logic:
• Zero, the ICS1892 isolates all STA writes to CW bits.
• One, an STA can modify the value of these bits.
8.3.7 MF Preamble Suppression (bit 1.6)
Status Register bit 1.6 is the Management Frame (MF) Preamble Suppression bit. The ICS1892 sets bit 1.6
to inform the STA of its ability to receive frames that do not have a preamble. When this bit is logic:
• Zero, the ICS1892 is indicating it cannot accept frames with a suppressed preamble.
• One, the ICS1892 is indicating it can accept frames that do not have a preamble.
Although the ICS1892 supports Management Frame Preamble Suppression, its default value for bit 1.6 is
logic zero. This default value ensures that bit 1.6 is backward compatible with the ICS 1890, which does not
have this capability. As the means of enabling this feature, bit 1.6 of the ICS1892 is a Command Override
Write bit, instead of a Read-Only bit as in the ICS 1890. An STA uses the bit 1.6 to enable MF Preamble
Suppression in the ICS1892. [See the description of bit 16.15, the Command Override Write Enable bit, in
Section 8.11, “Register 16: Extended Control Register”.]
8.3.8 Auto-Negotiation Complete (bit 1.5)
An STA reads bit 1.5 to determine the state of the ICS1892 auto-negotiation process. The ICS1892 sets the
value of this bit using two criteria. When its Auto-Negotiation sublayer is:
• Disabled, the ICS1892 sets bit 1.5 to logic zero.
• Enabled, the ICS1892 sets bit 1.5 to a value based on the state of the Auto-Negotiation State Machine.
When the Auto-Negotiation State Machine is enabled, it sets bit 1.5 to logic one only upon completion of
the auto-negotiation process. This setting indicates to the STA that a link is arbitrated and the contents of
Management Registers 4, 5 and 6 are valid. For more detailed information regarding the
auto-negotiation process, see Section 7.2, “Functional Block: Auto-Negotiation”.
Bit 1.5 is a latching high (LH) bit. (For more information on latching high and latching low bits, see Section
8.1.4.1, “Latching High Bits” and Section 8.1.4.2, “Latching Low Bits”.)
Note: An Auto-Negotiation Restart does not clear an LH bit.
ICS1892, Rev. D, 2/26/01
February 26, 2001
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
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ICS1892
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