ICS1892
10Base-T/100Base-TX Integrated PHYceiver™
TSD
Chapter 8 Management Register Set
ICS1892 Data Sheet
8.3.12 Jabber Detect (bit 1.1)
The purpose of this bit is to allow an STA to read this bit to determine if the ICS1892 detects a Jabber
condition.
The ISO/IEC specification defines the requirements for detection of a Jabber condition.To detect a Jabber
condition, the ICS1892 must first enable its Jabber Detection function, which is controlled by the Jabber
Inhibit bit in the 10Base-T Operations register (bit 18.5). When bit 18.5 is logic:
• Zero, the ICS1892 disables Jabber Detection
• One, the ICS1892 enables Jabber Detection. In this case, when the ICS1892 detects a Jabber condition,
it does the following:
– It sets bit 1.2 to logic one.
– It sets the Jabber Detect bit (bit 1.1 in the Status Register, and mirrored as bit 17.2 in the QuickPoll
Detailed Status Register) to logic one.
Bit 1.1 is a latching high (LH) bit. (For more information on latching high and latching low bits, see Section
8.1.4.1, “Latching High Bits” and Section 8.1.4.2, “Latching Low Bits”.)
8.3.13 Extended Capability (bit 1.0)
The STA reads bit 1.0 to determine if the ICS1892 has an extended register set. In the ICS1892 this bit is
always logic one, indicating that it has extended registers.
ICS1892, Rev. D, 2/26/01
February 26, 2001
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
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ICS1892
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