ICS1892
TSD
Chapter 8 Management Register Set
10Base-T/100BIaCseS-TX1I8nt9eg2rated PHYceiver™
8.2.2 Loopback Enable (bit 0.14)
This bit controls the Loopback mode for the ICS1892. Setting this bit to logic:
• Zero disables the Loopback mode.
• One enables the Loopback mode by disabling the Twisted-Pair Transmitter, the Twisted-Pair Receiver,
and the collision detection circuitry. (The STA can override the ICS1892 from disabling the collision
detection circuitry in Loopback mode by writing logic one to bit 0.7.) When the ICS1892 is in Loopback
mode, the data presented at the MAC/repeater transmit interface is internally looped back to the
MAC/repeater receive interface. The delay from the assertion of Transmit Data Enable (TXEN) to the
assertion of Receive Data valid (RXDV) is less than 512 bit times.
8.2.3 Data Rate Select (bit 0.13)
This bit provides a means of controlling the ICS1892 data rate. Its operation depends on the state of
several other functions, including the HW/SW input pin and the Auto-Negotiation Enable bit (bit 0.12).
When the ICS1892 is configured for:
• Hardware mode (that is, the HW/SW pin is logic zero), the ICS1892 isolates this bit 0.13 and uses the
10/100SEL input pin to establish the data rate for the ICS1892. In this Hardware mode:
– Bit 0.13 is undefined.
– The ICS1892 provides a Data Rate Status bit (in the QuickPoll Detailed Status Register, bit 17.15),
which always shows the setting of an active link.
• Software mode (that is, the HW/SW pin is logic one), the function of bit 0.13 depends on the
Auto-Negotiation Enable bit 0.12. When Auto-Negotiation is:
– Enabled, the ICS1892 isolates bit 0.13 and relies on the results of the auto-negotiation process to
establish the data rate.
– Disabled, bit 0.13 determines the data rate. In this case, setting bit 0.13 to logic:
• Zero selects 10-Mbps ICS1892 operations.
• One selects 100-Mbps ICS1892 operations.
8.2.4 Auto-Negotiation Enable (bit 0.12)
This bit provides a means of controlling the ICS1892 Auto-Negotiation sublayer. Its operation depends on
the HW/SW input pin.
When the ICS1892 is configured for:
• Hardware mode, (that is, the HW/SW pin is logic zero), the ICS1892 isolates bit 0.12 and uses the
ANSEL (Auto-Negotiation Select) input pin to determine whether to enable the Auto-Negotiation
sublayer.
Note: In Hardware mode, bit 0.12 is undefined.
• Software mode, (that is, the HW/SW pin is logic one), bit 0.12 determines whether to enable the
Auto-Negotiation sublayer. When bit 0.12 is logic:
– Zero:
• The ICS1892 disables the Auto-Negotiation sublayer.
• The ICS1892 bit 0.13 (the Data Rate bit) and bit 0.8 (the Duplex Mode bit) determine the data rate
and the duplex mode.
– One:
• The ICS1892 enables the Auto-Negotiation sublayer.
• The ICS1892 isolates bit 0.13 and bit 0.8.
ICS1892, Rev. D, 2/26/01
February 26, 2001
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
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IDT™ / ICS™ 10Base-T/100Base-TX Integrated PHYceiver™
ICS1892
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IDT [ INTEGRATED DEVICE TECHNOLOGY ]
