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IS61C512-15N 参数 Datasheet PDF下载

IS61C512-15N图片预览
型号: IS61C512-15N
PDF下载: 下载PDF文件 查看货源
内容描述: 64K ×8高速CMOS静态RAM [64K x 8 HIGH-SPEED CMOS STATIC RAM]
分类和应用: 存储内存集成电路静态存储器光电二极管
文件页数/大小: 8 页 / 425 K
品牌: ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
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IS61C512  
WRITE CYCLE NO. 2 (CE1, CE2 Controlled)(1,2)  
t
WC  
ADDRESS  
t
SA  
tHA  
t
SCE1  
CE1  
CE2  
t
SCE2  
t
AW  
t
PWE  
WE  
t
HZWE  
tLZWE  
HIGH-Z  
DOUT  
DATA UNDEFINED  
t
HD  
t
SD  
DIN  
DATA-IN VALID  
Notes:  
1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to  
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the  
rising or falling edge of the signal that terminates the write.  
2. I/O will assume the High-Z state if OE = HIGH.  
Integrated Circuit Solution Inc.  
7
SR011-0B