IS61C512
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-15 ns
Min.
-20 ns
-25 ns
Max.
-35 ns
Min.
Symbol Parameter
Max.
—
—
—
—
—
—
—
—
—
7
Min.
Max.
—
Min.
25
20
20
20
0
Max.
—
—
—
—
—
—
—
—
—
8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWC
Write Cycle Time
15
12
12
12
0
20
15
15
15
0
—
—
—
—
—
—
—
—
—
12
—
35
30
30
30
0
tSCE1
tSCE2
tAW
CE1 to Write End
—
CE2 to Write End
—
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
—
tHA
—
tSA
0
0
—
0
0
(4)
tPWE
tSD
WE Pulse Width
10
8
12
10
0
—
15
12
0
20
15
0
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
—
tHD
0
—
(2)
tHZWE
—
2
—
2
10
—
—
2
—
2
(2)
tLZWE
—
—
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
4. Tested with OE HIGH.
AC WAVEFORMS
WRITE CYCLE NO. 1 (WE Controlled)(1,2)
t
WC
ADDRESS
CE1
t
HA
t
SCE1
t
SCE2
CE2
t
AW
t
PWE
WE
t
SA
t
HZWE
t
LZWE
HIGH-Z
SD
DOUT
DATA UNDEFINED
t
t
HD
DATA-IN VALID
DIN
6
Integrated Circuit Solution Inc.
SR011-0B
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
