IC61LV5128
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-8
-10
Min.
10
-12
Min.
12
-15
Min.
15
10
10
Symbol Parameter
Min.
Max.
—
Max.
—
Max.
—
Max.
—
Unit
ns
tWC
tSCE
tAW
Write Cycle Time
8
7
7
CE to Write End
—
8
—
9
—
—
ns
Address Setup Time
to Write End
—
8
—
9
—
—
ns
tHA
Address Hold from Write End
Address Setup Time
0
0
—
—
—
—
—
4
0
0
—
—
—
—
—
5
0
0
—
—
—
—
—
6
0
0
—
—
—
—
—
7
ns
ns
ns
ns
ns
ns
ns
tSA
tPWE
tSD
WE Pulse Width
7
8
9
10
7
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
4.5
0
5
6
tHD
0
0
0
(2)
tHZWE
—
3
—
3
—
3
—
3
(2)
tLZWE
—
—
—
—
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
AC WAVEFORMS
WRITE CYCLE NO. 1 (1,2 )(CE Controlled, OE is HIGH or LOW)
t
WC
VALID ADDRESS
SCE
ADDRESS
CE
t
SA
t
t
HA
t
AW
t
t
PWE1
PWE2
WE
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
Integrated Circuit Solution, Inc.
AHSR021-0A 09/11/2001
7