IC42S16100
Write Cycle / Precharge Termination
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
t
CHI
t
CKS
t
CL
t
CK
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
t
AS
AS
tAH
(1)
(1)
COLUMN m
COLUMN n
AUTO PRE
ROW
ROW
ROW
A0-A9
t
t
AH
AH
ROW
A10
A11
NO PRE
BANK 1
BANK 0 OR 1
BANK 0
NO PRE
BANK 0
BANK 1
t
AS
BANK 0
BANK 0
t
CS
t
CH
BANK 0
CS
t
CS
t
CH
t
DQM
t
DH
DS
t
DH
DS
t
DH
tDH
t
DS
t
t
tDS
DIN 0m+2
DIN 0m+1
I/O
DIN 0m
DIN 0n
t
RCD
t
RCD
RAS
RC
t
t
RAS
t
t
RP
RC
t
<
PRE 0>
<
WRIT
>
>
<
ACT 0>
<
WRIT 0
>
<ACT >
<
WRITA
Undefined
Don’t Care
CAS latency = 2, burst length = 4
Note 1: A8,A9 = Don't Care.
Integrated Circuit Solution Inc.
55
DR024-0D 06/25/2004