IC42S16100
Write Cycle / Page Mode; Data Masking
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
t
CHI
t
CKS
t
CK
t
CL
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
(1)
t
t
AS
AS
tAH
(1)
(1)
COLUMN m
ROW
ROW
COLUMN n
COLUMN o
AUTO PRE
A0-A9
BANK 0 AND 1
BANK 1OR 0
t
t
AH
AH
NO PRE
BANK 1
NO PRE
BANK 1
A10
A11
NO PRE
t
AS
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
BANK 0
BANK 0
t
CS
tCH
DQM
t
DH
t
DS
t
DH
tDH
t
DS
t
DH
m
t
DS
t
DH
tDS
t
DS
D
IN
D
IN n
D
IN
o
D
IN o+1
D
IN m+1
I/O
t
RCD
t
DPL
t
RAS
RC
tRP
t
<
ACT
>
<
WRIT
>
<
WRIT
>
<MASK
>
<
WRIT
WRITA
>
<
PRE
PALL
>
<
>
<
>
Undefined
Don’t Care
CAS latency = 2, burst length = 2
Note 1: A8,A9 = Don't Care.
Integrated Circuit Solution Inc.
51
DR024-0D 06/25/2004
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
