IC42S16100
Read Cycle, Write Cycle / Burst Read, Single Write
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
t
CHI
t
CKS
t
CL
t
CK
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
(1)
(1)
t
t
AS
AS
tAH
COLUMN m
COLUMN n
AUTO PRE
ROW
ROW
A0-A9
BANK 0 AND 1
BANK 0 OR 1
t
t
AH
AH
NO PRE
BANK 1
A10
A11
NO PRE
t
AS
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
BANK 0
t
CS
t
CH
t
QMD
DQM
t
AC
t
AC
t
AC
t
AC
t
DS
t
OH
t
OH
t
OH
tOH
t
DH
I/O
DOUT
m
DOUT m+1
DOUT m+2
DOUT m+3
DIN n
t
LZ
t
HZ
t
RCD
t
CAC
tDPL
t
RAS
RC
t
RP
t
<
WRIT
WRITA
>
<
PRE
PALL
>
<
ACT
>
<READ>
<
>
<
>
Undefined
Don’t Care
CAS latency = 2, burst length = 4
Note 1: A8,A9 = Don't Care.
58
Integrated Circuit Solution Inc.
DR024-0D 06/25/2004
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
