IC42S16100
Read Cycle / Clock Suspend
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
t
CHI
t
CKS
t
CKS
tCKH
t
CL
t
CK
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
t
AS
AS
tAH
(1)
COLUMN m
AUTO PRE
ROW
ROW
ROW
A0-A9
BANK 0 AND 1
BANK 0 OR 1
t
t
AH
AH
ROW
A10
A11
NO PRE
BANK 1
t
AS
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
BANK 0
t
CH
t
CS
t
QMD
DQM
t
AC
t
AC
t
OH
t
OH
I/O
DOUT
m
DOUT m+1
t
LZ
t
HZ
t
RCD
tCAC
t
RAS
RC
t
RAS
RC
t
RP
t
t
<SPND
>
<SPND
>
<
PRE
PALL
>
<
ACT 0>
<
<
READ
>
>
<ACT >
<
>
READ A
Undefined
Don’t Care
CAS latency = 2, burst length = 2
Note 1: A8,A9 = Don't Care.
52
Integrated Circuit Solution Inc.
DR024-0D 06/25/2004