IC42S16100
Read Cycle / Page Mode; Data Masking
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
t
CHI
t
CKS
t
CK
t
CL
CKE
CS
t
t
CKA
CH
t
CS
t
CS
tCH
tCH
tCH
RAS
t
t
CS
CS
CAS
WE
t
t
AS
AS
tAH
(1)
(1)
(1)
COLUMN m
ROW
ROW
COLUMN n
COLUMN o
AUTO PRE
A0-A9
BANK 0 AND 1
BANK 0 OR 1
t
t
AH
AH
NO PRE
BANK 1
NO PRE
BANK 1
A10
A11
NO PRE
NO PRE
CH
t
AS
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
BANK 0
BANK 0
t
tQMD
t
CS
t
QMD
DQM
t
AC
t
AC
t
AC
t
AC
t
AC
t
OH
t
OH
m
t
OH
t
OH
tOH
I/O
D
OUT
D
OUT m+1
D
OUT
n
D
OUT
o
D
OUT o+1
t
LZ
tLZ
t
HZ
t
HZ
t
RCD
t
CAC
t
CAC
t
CAC
t
RQL
t
RAS
RC
t
RP
t
<
ACT
>
<
READ>
<MASK
>
<
READ, ENB
READA, ENB
>
<
PRE>
<
>
<PALL>
Undefined
Don’t Care
CAS latency = 2, burst length = 2
Note 1: A8,A9 = Don't Care.
Integrated Circuit Solution Inc.
49
DR024-0D 06/25/2004
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
