ICS1893BY-10 - Release
Chapter 9 DC and AC Operating Conditions
9.5.17 Reset: Power-On Reset
Table 9-24 lists the significant time periods for the power-on reset. The time periods consist of timings of
signals on the following pins:
• VDD
• TXCLK
Figure 9-18 shows the timing diagram for the time periods.
Table 9-24. Power-On Reset Timing
Time
Period
Parameter
Conditions
Min.
Typ. Max. Units
45 500 ms
t1
VDD ≥ 2.7 V to Reset Complete
–
40
Figure 9-18. Power-On Reset Timing Diagram
2.7 V
VDD
t1
TXCLK
Valid
ICS1893BY-10 Rev A 3/24/04
March, 2004
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
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