ICS1893BY-10 - Release
Chapter 9 DC and AC Operating Conditions
9.5.15 100M MII / 100M Stream Interface: Receive Latency
Table 9-22 lists the significant time periods for the 100M MII / 100M Stream Interface receive latency. The
time periods consist of timings of signals on the following pins:
• TP_RX (that is, TP_RXP and TP_RXN)
• RXCLK
• RXD (that is, RXD[3:0])
Figure 9-16 shows the timing diagram for the time periods.
Table 9-22. 100M MII / 100M Stream Interface Receive Latency Timing
Time
Parameter
Conditions
Min. Typ. Max.
Units
Period
t1
t2
First Bit of /J/ into TP_RX to /J/ on RXD 100M MII
–
–
16
8
17
9
Bit times
Bit times
First Bit of /J/ into TP_RX to /J/ on RXD 100M Stream Interface
Figure 9-16. 100M MII / 100M Stream Interface: Receive Latency Timing Diagram
TP_RX†
RXCLK
RXD
t1
t2
† Shown
unscrambled.
ICS1893BY-10 Rev A 3/24/04
March, 2004
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
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