ICS1893BY-10 Data Sheet - Release
Chapter 9 DC and AC Operating Conditions
9.5.18 Reset: Hardware Reset and Power-Down
Table 9-25 lists the significant time periods for the hardware reset and power-down reset. The time periods
consist of timings of signals on the following pins:
• REF_IN
• RESETn
• TXCLK
Figure 9-19 shows the timing diagram for the time periods.
Table 9-25. Hardware Reset and Power-Down Timing
Time
Period
Parameter
Condi-
tions
Min. Typ. Max. Units
t1
t2
t3
RESETn Active to Device Isolation and Initialization
Minimum RESETn Pulse Width
–
–
–
–
500
–
60
40
35
–
–
ns
ns
RESETn Released to TXCLK Valid
500
ms
Figure 9-19. Hardware Reset and Power-Down Timing Diagram
REF_IN
RESETn
t1
t2
t3
TXCLK Valid
Power
Consumption
(AC only)
ICS1893BY-10 Rev A 3/24/04
March, 2004
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
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ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
