ICS1893BY-10 - Release
Chapter 9 DC and AC Operating Conditions
9.5.13 100M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission)
Table 9-20 lists the significant time periods for the 100M MII carrier assertion/de-assertion during
half-duplex transmission. The time periods consist of timings of signals on the following pins:
• TXEN
• TXCLK
• CRS
Figure 9-14 shows the timing diagram for the time periods.
Table 9-20. 100M MII Carrier Assertion/De-Assertion (Half-Duplex Transmission Only)
Time
Period
Parameter
Condi- Min. Typ. Max. Units
tions
t1
t2
TXEN Sampled Asserted to CRS Assert
TXEN De-Asserted to CRS De-Asserted
0
0
3
3
4
4
Bit times
Bit times
Figure 9-14. 100M MII Carrier Assertion/De-Assertion Timing Diagram
(Half-Duplex Transmission Only)
t2
TXEN
TXCLK
CRS
t1
ICS1893BY-10 Rev A 3/24/04
March, 2004
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
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