ICS1893BY-10 Data Sheet - Release
Chapter 9 DC and AC Operating Conditions
9.5.10 10M Serial Interface: Transmit Latency
Table 9-17 lists the significant time periods for the 10M Serial Interface transmit latency. The time periods
consist of timings of signals on the following pins:
• 10TXEN (the 10M Serial Interface mapping of the 10M/100M MII TXEN pins)
• 10TCLK (the 10M Serial Interface mapping of the 10M/100M MII TXCLK pins)
• 10TD (the 10M Serial Interface mapping of the 10M/100M MII TXD0 pins)
• TP_TX (the MDI mapping of the 10M/100M MII TP_TXP and TP_TXN pins)
Figure 9-11 shows the timing diagram for the time periods.
Table 9-17. 10M Serial Interface Transmit Latency Timing
Time
Parameter
Conditions
Min. Typ. Max.
Units
Period
t1
10TD Into TP_TX Out Delay
10M Serial Interface
–
0.8
1
Bit times
Figure 9-11. 10M Serial Interface Transmit Latency Timing Diagram
10TXEN
10TCLK
10TD
Bit A
Bit B
(MDI)
P[3:0]TP_TX
Bit A
Bit B
t1
ICS1893BY-10 Rev A 3/24/04
March, 2004
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
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