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ICS1893BYI-10LF 参数 Datasheet PDF下载

ICS1893BYI-10LF图片预览
型号: ICS1893BYI-10LF
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3 -V的10Base -T / 100BASE - TX集成PHYceiver [3.3-V 10Base-T/100Base-TX Integrated PHYceiver]
分类和应用:
文件页数/大小: 143 页 / 1665 K
品牌: ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
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ICS1893BY-10 - Release  
Chapter 8 Pin Diagram, Listings, and Descriptions  
Table 8-6. MAC/Repeater Interface Pins: 100M Symbol Interface (Continued)  
MII Pin  
Name  
100M  
Symbol  
Pin  
Pin  
No.  
Pin  
Type  
Pin Description  
Name  
RXD0  
RXD1  
RXD2  
RXD3  
SRD0  
SRD1  
SRD2  
SRD3  
35  
34  
33  
32  
Output Symbol Receive Data 0–3.  
In 100M Symbol mode:  
The ICS1893BY-10’s SRD0 pin transmits the  
least-significant bit and the SRD4 pin transmits the  
most-significant bit of the symbol received from its  
MAC/Repeater interface.  
The ICS1893BY-10 continually transfers the data it receives  
from its MDI to its SRD[4:0] pins (that is, to its MAC/Repeater  
Interface). In the 100M Symbol mode, data is not framed.  
Therefore, the ICS1893BY-10 does not assert its RXDV  
signal.  
The ICS1893BY-10 transfers its receive data to the SRD[4:0]  
pins synchronously on the rising edges of its SRCLK signal.  
RXDV  
36  
No  
Receive Data Valid.  
Connect For the 100M Symbol Interface, this pin is a no connect. For  
more information, see Table 5-1.  
RXER  
RXTRI  
SRD4  
39  
41  
Output Symbol Receive Data 4.  
Input  
Receive (Interface), Tri-State.  
This pin’s input is from a MAC. When this pin’s signal is logic:  
Low, the MAC indicates it is not in a tri-state condition.  
High, the MAC indicates it is in a tri-state condition. In this  
case, the ICS1893BY-10 acts to ensure that only one PHY is  
active at a time. (A PHY address of 00 also tri-states the MII  
interface.)  
TXCLK  
STCLK  
43  
Output Symbol Transmit Clock.  
This pin’s description is the same as that given in Table 8-5.  
TXD0  
TXD1  
TXD2  
TXD3  
STD0  
STD1  
STD2  
STD3  
45  
46  
47  
48  
Input  
Symbol Transmit Data 0–3.  
In 100M Symbol mode:  
The ICS1893BY-10 STD0 pin receives the least-significant  
bit and the STD4 pin receives the most-significant bit of the  
symbol received from the MAC/Repeater interface.  
The signals on the ICS1893BY-10 STD[4:0] pins are  
continually and synchronously sampled on the rising edges  
of its STCLK. These signals are independent of the TXEN  
signal.  
Note: In 100M Symbol mode, TXEN is not used because the  
MAC/Repeater is responsible for sending both IDLE  
symbols and data.  
TXEN  
TXER  
44  
42  
No  
Transmit Enable.  
Connect For the 100M Symbol Interface, this pin is a no connect. For  
more information, see Table 5-1.  
STD4  
Input  
Symbol Transmit Data 4.  
This pin’s description is the same as that given in Table 8-5.  
ICS1893BY-10 Rev A 3/24/04  
March, 2004  
Copyright © 2004, Integrated Circuit Systems, Inc.  
All rights reserved.  
111  
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