ICS1893BY-10 Data Sheet - Release
Chapter 8 Pin Diagram, Listings, and Descriptions
Table 8-5. MAC/Repeater Interface Pins: Media Independent Interface (MII) (Continued)
Pin
Pin
Pin
Pin Description
Name Number
Type
RXCLK
38
Output Receive Clock.
The ICS1893BY-10 sources the RXCLK to the MAC/repeater interface.
The ICS1893BY-10 uses RXCLK to synchronize the signals on the
following pins: RXD[3:0], RXDV, and RXER. The following table contrasts
the behavior on the RXCLK pin when the mode for the ICS1893BY-10 is
either 10Base-T or 100Base-TX.
10Base-T
100Base-TX
The RXCLK frequency is 2.5
MHz.
The RXCLK frequency is 25 MHz.
The ICS1893BY-10 generates its The ICS1893BY-10 generates its
RXCLK from the MDI data stream RXCLK from the MDI data stream
using a digital PLL. When the MDI while there is a valid link (that is,
data stream terminates, the PLL
continues to operate,
either data or IDLEs). In the
absence of a link, the
synchronously referenced to the
last packet received.
ICS1893BY-10 uses the REF_IN
clock to generate the RXCLK.
The ICS1893BY-10 switches
While the ICS1893BY-10 is
between clock sources during the bringing up a link, a clock phase
period between when its CRS is
asserted and prior to its RXDV
being asserted. While the
change of up to 360 degrees can
occur.
ICS1893BY-10 is locking onto the
incoming data stream, a clock
phase change of up to 360
degrees can occur.
The RXCLK aligns once per
packet.
The RXCLK aligns once, when
the link is being established.
Note: The signal on the RXCLK pin is conditioned by the RXTRI pin.
Output Receive Data 0–3.
RXD0
RXD1
RXD2
RXD3
35
34
33
32
• RXD0 is the least-significant bit and RXD3 is the most-significant bit of
the MII receive data nibble.
• While the ICS1893BY-10 asserts RXDV, the ICS1893BY-10 transfers
the receive data signals on the RXD0–RXD3 pins to the
MAC/Repeater Interface synchronously on the rising edges of RXCLK.
RXDV
36
Output Receive Data Valid.
The ICS1893BY-10 asserts RXDV to indicate to the MAC/repeater that
data is available on the MII Receive Bus (RXD[3:0]). The ICS1893BY-10:
• Asserts RXDV after it detects and recovers the Start-of-Stream
delimiter, /J/K/. (For the timing reference, see Chapter 9.5.6, “MII /
100M Stream Interface: Synchronous Receive Timing”.)
• De-asserts RXDV after it detects either the End-of-Stream delimiter
(/T/R/) or a signal error.
Note: RXDV is synchronous with the Receive Data Clock, RXCLK.
ICS1893BY-10 Rev A 3/24/04
March, 2004
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
108
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
