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ICS1572M-101 参数 Datasheet PDF下载

ICS1572M-101图片预览
型号: ICS1572M-101
PDF下载: 下载PDF文件 查看货源
内容描述: 用户可编程差分输出图形时钟发生器 [User Programmable Differential Output Graphics Clock Generator]
分类和应用: 晶体时钟发生器外围集成电路光电二极管
文件页数/大小: 19 页 / 279 K
品牌: ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
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ICS1572  
Pin Descriptions - ICS1572-101  
PIN#  
NAME  
DESCRIPTION  
13  
12  
8
CLK+  
CLK−  
LOAD  
XTAL1  
XTAL2  
AD0  
Clock out (non-inverted)  
Clock out (inverted)  
Load output. This output is normally at the CLK frequency divided by N1.  
Quartz crystal connection 1/external reference frequency input  
Quartz crystal connection 2  
3
4
2
Address/Data Bit 0 (LSB)  
19  
18  
17  
9
AD1  
Address/Data Bit 1  
AD2  
Address/Data Bit 2  
AD3  
Address/Data Bit 3 (MSB)  
LD/N2  
STROBE  
VDD  
Divided LOAD output. See text.  
5
Control for address/data latch  
16  
15  
14  
6,7  
PLL system power (+5V. See application diagram.)  
Output stage power (+5V)  
VDDO  
IPRG  
VSS  
Output stage current set  
Device ground. Both pins must be connected to the same ground potential.  
Not connected  
1,10,11,20  
NC  
Pin Descriptions - ICS1572-301  
PIN#  
NAME  
DESCRIPTION  
13  
12  
8
CLK+  
CLK−  
LOAD  
XTAL1  
XTAL2  
DATCLK  
DATA  
HOLD~  
BLANK  
LD/N2  
EXTFBK  
VDD  
Clock out (non-inverted)  
Clock out (inverted)  
Load output. This output is normally at the CLK frequency divided by N1.  
Quartz crystal connection 1/external reference frequency input  
Quartz crystal connection 2  
3
4
5
Data Clock (Input)  
19  
18  
17  
9
Serial Register Data (Input)  
HOLD (Input)  
Blanking (Input). See Text.  
Divided LOAD output/shift clock. See text.  
External feedback connection for PLL (input). See text.  
PLL system power (+5V. See application diagram.)  
Output stage power (+5V)  
2
16  
15  
14  
6,7  
VDDO  
IPRG  
Output stage current set  
VSS  
Device ground. Both pins must be connected.  
Not connected  
1,10,11,20  
NC  
13