IC-MR 参数 Datasheet PDF下载

iC-MR

13-BIT S&H SIN/COS

preliminar y

Rev A1, Page 9/44

INTERPOLATOR WITH CONTROLLER INTERFACES

ELECTRICAL CHARACTERISTICS

Operating conditions:

VDDA = VDD = 4.5...5.5 V, GNDA = GND = 0 V, IBP calibrated to 200 µA, Tj = -40...125 °C, unless otherwise noted.

Item

No.

Symbol

Parameter

Conditions

Min.

Conversion Time

Absolute Conversion Accuracy

VDD Turn-on Threshold

VDD Turn-off Threshold

VDD Hysteresis

Input Threshold Voltage hi

Input Threshold Voltage lo

Input Hysteresis

Pull-up Current

Output Saturation Voltage lo

Output Short-Circuit Current lo

Internal Oscillator Frequency

Saturation voltage lo

Short-Circuit Current lo

Input Threshold Voltage hi

Input Threshold Voltage lo

Input Hysteresis

Input Pull-up Current

Input Pull-up Voltage

Clock Frequency at SCL

Duration of Configuration Phase

IBP not adjusted;

read in of EEPROM

no EEPROM connected

Vt()hys = Vt()hi - Vt()lo

V() = 0 V...VDD - 1 V

Vpu() = VDD - V(), I() = -5 µA

100

120

5

1

2

0.8

Vt()hys = Vt()hi - Vt()lo

300

-150

8

SSI protocol

BiSS C protocol

SPI

10

ACQMODE = 00, see Figure 5

t()ipo

1/fosc

1.5*t

MAS

+

3/fosc

400

400

-80

4

-4

80

2

0.8

300

-70

500

-30

-5

mV

mV

mA

mA

V

V

mV

µA

500

-60

60

-8

150

4

10

10

50

0.8

100

-750

250

-300

-60

0.4

130

I() = 4 mA

4

I() = 4 mA

V() = 0.4 V...VDD

4

15

400

80

2

Vt()hys = Vt()hi - Vt()lo

0.8

300

-750

500

-300

-60

400

80

ACQMODE = 00, see Figure 5

Vpk() = 250 mV

increasing voltage at VDD vs. GND

decreasing voltage at VDD vs. GND

VDDhys = VDDon - VDDoff

2.6

2.3

400

2

Typ.

2

2

4.3

4.0

Max.

µs

LSB

V

V

mV

V

V

mV

µA

mV

mA

MHz

mV

mA

V

V

mV

µA

V

kHz

ms

ms

V

V

mV

µA

µA

MHz

MHz

MHz

ns

Unit

13-bit Interpolator

C01 tipo

C02 AAabs

K01

K02

K03

K04

K05

K06

K07

K08

K09

VDDon

VDDoff

VDDhys

Vt()hi

Vt()lo

Vt()hys

Ipu()

Vs()lo

Isc()lo

Reset Input / Reset Indication Output NRES

Oscillator

M01 fosc

N01 Vs()lo

N02 Isc()

N03 Vt()hi

N04 Vt()lo

N05 Vt()hys

N06 Ipu()

N07 Vpu()

N08 fclk()

N09 tbusy()cfg

EEPROM Interface SCL, SDA

Serial Interface MAI, SLO, SLI

O01 Vt()hi

O02 Vt()lo

O03 Vt()Hys

O04 Ipu()

O05 Ipd()

O06 fclk()

Threshold Voltage hi at SLI, MAI

Threshold Voltage lo at SLI, MAI

Hysteresis at SLI, MAI

Pull-up Current at MAI

Pull-down Current at SLI

Permissible Clock Frequency at

MAI

Propagation Delay at SLO versus

Clock Edge MAI

Processing Time

Adaptive Timeout

O07 tp()

O08 tbusy()

O09 t

timeout

O10 Vs()hi

O11 Vs()lo

O12 Isc()hi

O13 Isc()lo

P01

P02

P03

P04

Vt()hi

Vt()lo

Vt()hys

Ipu()

Saturation Voltage hi at SLO

Saturation Voltage lo at SLO

Short-circuit Current hi at SLO

Short-circuit Current lo at SLO

Threshold Voltage hi

Threshold Voltage lo

Input Hysteresis

Pull-up Current at D(7...0)

Vs()hi = VDD - V(), I() = -4 mA

I() = 4 mA

V() = 0 V...VDD - 0.4 V

V() = 0.4 V...VDD

D(7...0) as input

D(7...0) as input

D(7...0) as input, Vt()hys = Vt()hi - Vt()lo

Parallel Interface D(7...0), NWR, NRD, NL, NCS